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Addressing Technique for Dynamic Memory

IP.com Disclosure Number: IPCOM000052851D
Original Publication Date: 1981-Jul-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Davis, TH: AUTHOR [+2]

Abstract

One technique for a memory architecture requires 16K bytes of unpaged memory and from 1 to 7 additional 16K-byte blocks of paged memory. This may be implemented by using, for example, an Intel 8202 dynamic random-access memory controller such as shown in the figure. Under normal circumstances the controller is capable of controlling 64K bytes of unpaged memory.

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Addressing Technique for Dynamic Memory

One technique for a memory architecture requires 16K bytes of unpaged memory and from 1 to 7 additional 16K-byte blocks of paged memory. This may be implemented by using, for example, an Intel 8202 dynamic random-access memory controller such as shown in the figure. Under normal circumstances the controller is capable of controlling 64K bytes of unpaged memory.

To both increase the memory size and provide for paging techniques controlled by page bits 0, 1 and 2 from the central processor, the controller is arranged so that the row access selector zero (RAS 0) line is used for unpaged memory and the RAS 1 line is used for paged memory. This, in turn, may be controlled by the logic value of the signal applied to the B0 input of the controller. In addition, the column access strobe (CAS) line is used directly for unpaged memory and is gated with the output of a 3 to 8 decoder (which decodes the page 0, 1 and 2 bits into one of eight signals) to produce separate CASl through CAS7 lines for each of the seven paged areas.

This approach resolves the problem that the controller is designed to handle addressing for only 64K bytes of memory and divides the memory bank into 8 areas with the added distinction between paged and unpaged memory.

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