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Hardware Synchronization of a Low Performance Local Storage Device with a High Performance Microprocessor

IP.com Disclosure Number: IPCOM000052853D
Original Publication Date: 1981-Jul-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 5 page(s) / 97K

Publishing Venue

IBM

Related People

Cannon, JW: AUTHOR [+2]

Abstract

A local storage array with a Read/Write cycle time is incorporated into a microprocessor having a shorter cycle time. A hardware interface is provided for synchronizing the storage array with a processor.

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Hardware Synchronization of a Low Performance Local Storage Device with a High Performance Microprocessor

A local storage array with a Read/Write cycle time is incorporated into a microprocessor having a shorter cycle time. A hardware interface is provided for synchronizing the storage array with a processor.

The microcode structure of the processor designates a destination for the storage of the data resulting from an ALU operation and a next source of data for the next ALU operation. Of the possible destinations and next sources, 75% involve a local storage operation. In a representative system, perhaps 12% of the microcode instructions have both a destination and a next source involving local storage.

In Fig. 1, a Write cycle consists of a clock time and a recovery time for a total time. A Read cycle also consists of a clock time and a recovery time for a total cycle time. A total of each time is required to complete a write and a read which is the requirement of the processor microcode. Fig. 2 shows the processor cycle as consisting of three time intervals, A, B, and C time, each having a fixed duration. Because the frequency of this oscillator allows resolutions in clocks of no less than one time interval, each clock time and recovery time must be one time interval and the Write and Read cycle combination must consist of four time intervals. However, the total processor cycle is only three time intervals in duration, and an extra time interval added to the processor cycle for 12% of the instructions would impact the performance of the processor.

The basic operation of the processor is centered around the Arithmetic and Logic Unit (ALU). As already stated, the results of the ALU operation are stored in the various destinations available. The propagation delay through the ALU is such that the resultant data is available during C time, provided that the next source data is present during A time of the same cycle.

The solution to this problem takes advantage of a principal function of the random-access memory. When a Read cycle clock time has been completed, the data is loaded into an internal register and is not viewed at the output of the random-access memory until a signal called Output Enable is activated. This gate controls the output data in this manner regardless of what operations are in progress in the random-access memory. Therefore, next source data can be made available to the processor during the same time that destination data is being written into local storage. This function is used to allow the next source to be read at any time available during a processor cycle and gated out of the random-access memory during A time of the following cycle.

Similarly, it is possible to write the destination data into local storage during the next processor cycle if the data and address are saved in a set of latches. This added versatility gives the interface twice as many sequential write and read combinations before it has to a...