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Permanent Breakpoints Using Hardware Trace

IP.com Disclosure Number: IPCOM000052854D
Original Publication Date: 1981-Jul-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Bowdry, RJ: AUTHOR [+2]

Abstract

This mechanism provides permanent program breakpoints in a relatively simple manner and without performance degradation.

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Permanent Breakpoints Using Hardware Trace

This mechanism provides permanent program breakpoints in a relatively simple manner and without performance degradation.

An accepted method of providing software breakpoints is to replace the first two bytes of an instruction with a supervisor call (SVC) instruction while saving the replaced two bytes. When the SVC instruction is encountered during program execution, the debugging facility will gain control. After breakpoint, processing is completed, the SVC instruction is replaced by the original two bytes and program execution resumes. Unfortunately, this means that the breakpoint is removed after one use.

The new mechanism described herein provides permanent breakpoints. After gaining control in the SVC routine and before allowing execution of the problem program to resume, this new mechanism does the following: It sets a first time switch in the debug program to zero and turns on the hardware trace bit in the level status register contained in the saved level status block of the problem program. When program execution resumes, a hardware trace interrupt will occur. If the first time switch is equal to zero, this means the restored instruction is not about to be executed. In this case, the location of the instruction is saved, the first time switch is set to 1 and execution is resumed with the hardware trace still on for the problem program, but with the inhibit trace bit on in the level status block. This will cause...