Browse Prior Art Database

Maximized LSSD Test I/O Pin Usage

IP.com Disclosure Number: IPCOM000052855D
Original Publication Date: 1981-Jul-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Whitley, WP: AUTHOR

Abstract

This technique enables additional tests to be performed on an integrated circuit chip by means of the same chip I/O pins as are presently used for normal level sensitive scan design (LSSD) testing of the chip. This is done by providing multiplexing circuitry on the chip for enabling additional test points to be connected to one of the LSSD test I/O pins when LSSD tests are not being performed. Other existing LSSD I/O pins are used to control the multiplexing circuitry.

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Maximized LSSD Test I/O Pin Usage

This technique enables additional tests to be performed on an integrated circuit chip by means of the same chip I/O pins as are presently used for normal level sensitive scan design (LSSD) testing of the chip. This is done by providing multiplexing circuitry on the chip for enabling additional test points to be connected to one of the LSSD test I/O pins when LSSD tests are not being performed. Other existing LSSD I/O pins are used to control the multiplexing circuitry.

Fig. 1 shows the on-chip multiplexing circuitry for accomplishing this purpose. Nodes 10, 11 and 12 represent existing chip I/O pins which are used for normal LSSD testing. In the normal LSSD test mode, an external shift gate signal is supplied to pin 12 to place it at the binary 1 level. This enables the serial data bits from the on-chip shift register latch (SRL) string to be passed by way of AND circuit 13 and OR circuit 14 to the Scan Data Out pin 11. This supplies the serial data bits to the external LSSD test equipment.

The multiplexing circuitry represented by multiplexer 15, AND circuit 16 and NOT circuit 17 enables a goodly number of additional on-chip test point signals TP1, TP2, .... TPX to be supplied to the Scan Data Out pin 11 during non-LSSD test intervals. In particular, for the non-LSSD tests, the Shift Gate pin 12 is placed at the binary 0 level to deactivate the AND circuit 13 and instead to enable the AND circuit 16 to pass signals from the multiplexer 15 to the OR circuit 14 and, hence, to the l/O pin 11. I...