Browse Prior Art Database

Flexible Tape Conductor Interconnection for Chips

IP.com Disclosure Number: IPCOM000052866D
Original Publication Date: 1981-Jul-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Auletta, LV: AUTHOR [+2]

Abstract

In the packaging of semiconductor chips it is often desirable to interconnect memory chips both to other memory chips and to processor or control chips. This article describes a technique for such interconnection.

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Flexible Tape Conductor Interconnection for Chips

In the packaging of semiconductor chips it is often desirable to interconnect memory chips both to other memory chips and to processor or control chips. This article describes a technique for such interconnection.

As shown in Figs. 1, 2 and 3, a substrate material, such as a polyimide plastic, is utilized having a top surface 12 and a bottom surface 14. The top surface 12 is provided with a series of in-line chip connection sites 16 each comprised of a plurality of solder balls 18. A series of metal lines 20 and 22 are provided, the lines 20 interconnecting the solder balls 18 at adjacent sites 16 and the lines 22 providing common connections to input-output terminals.

Conventional silicon semiconductor chips 24 are solder bonded to the solder balls 18 at the various sites 16 to provide a series of in-line chips.

The bottom surface 14 has deposited thereon ground isolation lines 25 which are connected through metal-filled vias 26 to selected lines 20 or 22 on the top surface 12. However, the location of the ground lines is not limited to bottom surface 14 but can also be interspersed between lines on other surfaces.

Fig. 4 shows a modification of the embodiment of Figs. 1, 2, and 3. In this embodiment a pair of substrates 30, 32 having in-line chip configurations, as described, above are interconnected to a common processor or control chip 34.

This technique is also applicable to multilayer substrates formed of ei...