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Method to Greatly Increase the Wirability of Semiconductor Logic Chips

IP.com Disclosure Number: IPCOM000052885D
Original Publication Date: 1981-Jul-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Shott, FA: AUTHOR [+2]

Abstract

Logic design engineers generally interconnect basic circuit/cell blocks based on logic function and timing needs and without regard to the physical placement of these blocks into the semiconductor.

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Method to Greatly Increase the Wirability of Semiconductor Logic Chips

Logic design engineers generally interconnect basic circuit/cell blocks based on logic function and timing needs and without regard to the physical placement of these blocks into the semiconductor.

The placement of a block on a chip is determined mathematically on the basis of interconnection priority, physical, electrical and technological constraints. Therefore, the loginacal interconnection must be defined before placement can be done, but within the resulting logic interconnection and physical layout scheme, there are many instances where equivalent nets can be interchanged to reduce interconnection wiring requirements, thereby improving wirability which results eventually in more circuit and function capability per a given silicon area.

The procedure outlined below greatly improves the process.

1. Equivalent nets are identified and verified. This can be done manually by the logic designer (examples are large fanout load cells, non-critical timing paths which are sources to many other circuits, etc.) or automatically by software algorithms which identify equivalent nets from the logic data base and use logical rules to verify equivalency.

2. The chip is placed utilizing conventional placement programs and algorithms and a data base output which contains logic, interconnection and physical position data.

3. The results of step 1 are used with step 2 to swap logical nets around to reduce int...