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Contact First FET Technology

IP.com Disclosure Number: IPCOM000052901D
Original Publication Date: 1981-Jul-01
Included in the Prior Art Database: 2005-Feb-12
Document File: 4 page(s) / 90K

Publishing Venue

IBM

Related People

Garbarino, PL: AUTHOR [+2]

Abstract

A method of doping and passivating the contact polycrystalline silicon or Poly I layer 10 involves implanting As or P at the doping level of about 3 x 10/16/cm/2/ and at low energies into the upper reaches of the contact polysilicon layer 10. A chemical vapor deposited (CVD) silicon dioxide layer 11 is then deposited on Poly I layer 10 of such thickness that the final thickness of that layer after gate silicon dioxide growth is 3000-4000 angstroms. This is done to minimize overlap capacitances between the poly layers after polycrystalline silicon or Poly II layer 12 is formed on the silicon dioxide layer 11, as shown in Fig. 1.

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Contact First FET Technology

A method of doping and passivating the contact polycrystalline silicon or Poly I layer 10 involves implanting As or P at the doping level of about 3 x 10/16/cm/2/ and at low energies into the upper reaches of the contact polysilicon layer 10. A chemical vapor deposited (CVD) silicon dioxide layer 11 is then deposited on Poly I layer 10 of such thickness that the final thickness of that layer after gate silicon dioxide growth is 3000-4000 angstroms. This is done to minimize overlap capacitances between the poly layers after polycrystalline silicon or Poly II layer 12 is formed on the silicon dioxide layer 11, as shown in Fig. 1.

Alternatively, a composite insulator of SiO(2) (about 3000 angstroms) layer 15 and Si(3)N(4) (about 40O angstroms) layer 16 may be used to reduce the Poly I layer 10 to Poly II layer 12 overlap capacitance. The function of the silicon nitride layer 16 is to prevent the oxidation of the contact polycrystalline silicon or Poly I layer 10 while a thick (about 4000 angstroms) silicon dioxide layer 17 is grown on Poly II layer 12. To reduce heat treatment (time at temperature), this deposition thickness of the Poly II layer 12 is increased to compensate for the silicon consumed during the thick oxidation. As shown in Fig. 2, the net effect of such oxidation is to reduce the Poly I layer 10, Poly II layer 12 overlap area and hence the capacitance.

The contact polycrystalline silicon layer 10 provides a layer of interconnection. lts usefulness in that capacity depends on its resistivity. The phosphorus implant of the dosage given in the above paragraph gives a resistivity, rho, at 3500 angstroms thickness of about 15 ohms square when subjected to temperatures of 1000 degrees C or more. This is lower than what is commonly attained for phosphosilicate glass doping. Arsenic does not give as low a resistivity, rho, as phosphorus at the same or any ion dosage.

If necessary in a particular application, the contact polycrystalline silicon layer 10 can be formed using a first metal or any other wiring level. By insuring that the silicon dioxide layer 20 or Poly I layer 21 is thinner than the silicon dioxide layer 23 on Poly II layer 22, a contact 24 to Poly 1 layer 21 may be allowed to overlap Poly II layer 22 at design or in the tolerance of the design, as shown in Fig. 3. A directional dry etch of the silicon dioxide layer 20 on Poly I layer 21 will allow a contact opening to the Poly I layer without requiring that the contact be solely over the recessed silicon dioxide region 25. Such a requirement would necessitate a larger...