Browse Prior Art Database

Electroless Plated Spacer Technology

IP.com Disclosure Number: IPCOM000052909D
Original Publication Date: 1981-Jul-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Revitz, M: AUTHOR [+2]

Abstract

N- regions 10 are produced by diffusion or ion implantation in a silicon substrate 12 using a polysilicon layer l4 with silicon dioxide layer 15 thereon for self-alignment, as shown in Fig. 1. A technique to produce spacers on the sides of the polysilicon land 14 is to electrolessly plate a material such as nickel or comparable materials thereon. It is possible to plate these materials only on the polysilicon sidewalls and not on the remaining non-polysilicon surfaces. After the formation of spacers 16 by this technique, a second N+ diffusion or ion implantation can be used to form source/drain regions 18, as shown in Fig. 2.

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Electroless Plated Spacer Technology

N- regions 10 are produced by diffusion or ion implantation in a silicon substrate 12 using a polysilicon layer l4 with silicon dioxide layer 15 thereon for self-alignment, as shown in Fig. 1. A technique to produce spacers on the sides of the polysilicon land 14 is to electrolessly plate a material such as nickel or comparable materials thereon. It is possible to plate these materials only on the polysilicon sidewalls and not on the remaining non-polysilicon surfaces. After the formation of spacers 16 by this technique, a second N+ diffusion or ion implantation can be used to form source/drain regions 18, as shown in Fig. 2.

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