Browse Prior Art Database

High Density Planar Metal Lands

IP.com Disclosure Number: IPCOM000052911D
Original Publication Date: 1981-Jul-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 3 page(s) / 73K

Publishing Venue

IBM

Related People

Barson, F: AUTHOR [+3]

Abstract

It is known that closely spaced metal lands, to shrink the size of bipolar transistors, may be achieved by using N+ polysilicon and etching, as will be described with regard to Figs. 1-4. As shown in Fig. 1, N+ polysilicon is applied over the transistor and is then etched away from the base and other unwanted regions. A CVD (chemical vapor deposition) oxide, such as SiO(2), is then deposited over the wafer, as shown in Fig. 2. Thereafter, a blanket RIE (reactive ion etching) is undertaken to remove the oxide everywhere except at the sides of the polysilicon, and then the polysilicon is removed. This is shown in Fig. 3.

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High Density Planar Metal Lands

It is known that closely spaced metal lands, to shrink the size of bipolar transistors, may be achieved by using N+ polysilicon and etching, as will be described with regard to Figs. 1-4. As shown in Fig. 1, N+ polysilicon is applied over the transistor and is then etched away from the base and other unwanted regions. A CVD (chemical vapor deposition) oxide, such as SiO(2), is then deposited over the wafer, as shown in Fig. 2. Thereafter, a blanket RIE (reactive ion etching) is undertaken to remove the oxide everywhere except at the sides of the polysilicon, and then the polysilicon is removed. This is shown in Fig. 3. Finally, a blanket metal is sputtered or evaporated on the device with oxide sidewalls, and a planarization process is then performed with photoresist and RIE so as to achieve the planarized configuration shown in Fig. 4.

Although not obvious from the cross-sectional drawings shown, a basic problem exists in making interconnections with the above described process. In the top view shown in Fig. 5, the shaded areas represent the N+ polysilicon remaining in contact with the N+ regions of the transistor. In addition, the SiO(2) sidewalls built up by the CVD deposition are also shown. When the polysilicon is removed by preferential etching and metallization is added, as shown in Fig. 6, it can be seen that the shaded regions shown in Fig. 5 are successfully filled to form extended metal lands, separated from each other by oxide barriers. However, all the remaining metal regions, including the base contact at B, are interconnected with each other.

Two methods are proposed to make the above-described process feasible and yet isolate portions of the remaining interconnected metal. The first method involves introducing additional thin oxide sidewalls in the same way as was...