Browse Prior Art Database

Hardware Technique for Obtaining Correction Parameters of a Subfield Writing System

IP.com Disclosure Number: IPCOM000052912D
Original Publication Date: 1981-Jul-01
Included in the Prior Art Database: 2005-Feb-12
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Ainsworth, RA: AUTHOR [+2]

Abstract

In a ""vector subfield'' deflection system, a calibration procedure is provided to measure and correct the beam positioning distortion. Distortions are measured at the corners of every subfield by scanning a fixed calibration grid of marks, of known characteristics, at the corners of each subfield.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 76% of the total text.

Page 1 of 2

Hardware Technique for Obtaining Correction Parameters of a Subfield Writing System

In a ""vector subfield'' deflection system, a calibration procedure is provided to measure and correct the beam positioning distortion. Distortions are measured at the corners of every subfield by scanning a fixed calibration grid of marks, of known characteristics, at the corners of each subfield.

The corrections (SC(x), SC(y)) at any point within any subfield is given by: ## See Original

These correction parameters are calculated from the measured errors at the corners of each subfield as follows:

If delta x(1), delta x(2), delta x(3), and delta x(4) represent the horizontal corner errors at a given subfield, then: ## See Original where a, b, c, and d are constants dependent on the subfield size and may be combined with the scale factors of correction hardware and used by a software program to determine the digital word input to correction generation hardware for each subfield. As a result, Equation 2 reduces to: ## See Original

Similar equations apply also for vertical errors.

Equation 3 can now be generated by hardware as follows: Measured displacement values and/or error indicators are delivered serially and are loaded sequentially in registers 1 through 4, in the figure. The internal logic circuits check to determine if any of the four incoming values are error indicators. If not, output registers 5 through 8 (A(i) through D(i)) are loaded after a sufficient time has elapsed...