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Method to Fabricate NPN Transistors Involving Totally Non-Critical Mask Registrations

IP.com Disclosure Number: IPCOM000052914D
Original Publication Date: 1981-Jul-01
Included in the Prior Art Database: 2005-Feb-12
Document File: 6 page(s) / 130K

Publishing Venue

IBM

Related People

Jambotkar, CG: AUTHOR

Abstract

A method is described for fabricating NPN bipolar transistors for integrated circuits. The main feature of the method is that it eliminates the need to register a mask in a critical manner relative to the patterns already created on wafer substrates during processing. In designing mask geometries, allowance is then no longer necessary for normal mask misregistrations. As a consequence, the NPN transistors require smaller chip area. Further, the electrical characteristics of the transistors also possess a tighter tolerance.

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Method to Fabricate NPN Transistors Involving Totally Non-Critical Mask Registrations

A method is described for fabricating NPN bipolar transistors for integrated circuits. The main feature of the method is that it eliminates the need to register a mask in a critical manner relative to the patterns already created on wafer substrates during processing. In designing mask geometries, allowance is then no longer necessary for normal mask misregistrations. As a consequence, the NPN transistors require smaller chip area. Further, the electrical characteristics of the transistors also possess a tighter tolerance.

The sequential processing method is as follows:

Starting with a P/-/ type wafer 2 as substrate, a blanket N/+/ layer 4 is formed at its surface through a conventional diffusion technique or ion implantation and drive-in, as shown in Fig. 1. A 1-2 mum thick N/-/ type layer of silicon 6 is then epitaxially grown at the wafer surface.

The above steps are followed by the thermal growth of a layer about 160O angstroms thick of SiO(2), as shown partially at 8, and chemical vapor deposition (CVD) of about 140O angstroms of Si(3)N(4), as shown partially at 10. conventional masking and reactive ion etching (RIE) techniques, suitable patterns are formed in the SiO(2) 8/Si(3)N(4) 10 composite and about 5000 angstroms thick polysilicon 12 is then deposited on the substrate.

Using photoresist mask 13, P region 14 is formed near the surface of polysilicon 12, as shown in Fig. 1, through ion implantation. Using another photoresist mask, identified as 15 in Fig. 2, N region 16 is then formed through ion implantation also near the surface of polysilicon layer 12. The cross-section of the NPN transistor at this stage of processing is shown in Fig. 2.

Following deposition of about 600 angstroms thick Si(3)N(4) 18, photoresist mask 19, as shown in Fig. 3, is formed at the wafer surface. One then proceeds to replicate the images of photoresist mask 19 in the composite of Si(3)N(4) 18 and polysilicon 12 layers, as depicted in Fig. 3. RIE is used for the purpose of this replication.

Keeping photoresist mask 19 intact, a new layer of photoresist 21 is coated on the substrate and patterned in a conventional manner, as shown in Fig. 4. The next process step consists of forming 2-4 mum deep trenches in exposed silicon, according to the illustration in Fig. 4. RIE is exploited for this purpose using gases which etch silicon anisotropically while allowing photoresist patterns 19 and 21 to serve as effective masks.

All photoresist is now stripped and about 50O angstroms thick layer of SiO(2) is thermally grown at the exposed silicon surface. Like all other non-critical masks, a new registrationwise non-critical photoresist mask is formed at this stage. It covers all substrate surface excepting the deep trench regions mentioned earlier. This mask is used to implant P type ions specifically at the bottom surface of the deep trenches, as shown at 24 in Fig. 5....