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Buried Gate Electrically Alterable Memory Device

IP.com Disclosure Number: IPCOM000052919D
Original Publication Date: 1981-Aug-01
Included in the Prior Art Database: 2005-Feb-12
Document File: 2 page(s) / 83K

Publishing Venue

IBM

Related People

Tsang, YL: AUTHOR

Abstract

In many designs for electrically alterable (EA) memory devices, much of the area is occupied by the programming gate and floating gate overlap due to the requirement for higher capacitive coupling. In such designs, the respective gate materials are laid on planes parallel to the wafer surface. This type of topology would demand more surface area if higher coupling is needed [1,2]. To overcome this constraint, folding can be introduced in portions of the device to introduce area-saving vertical geometric features.

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Buried Gate Electrically Alterable Memory Device

In many designs for electrically alterable (EA) memory devices, much of the area is occupied by the programming gate and floating gate overlap due to the requirement for higher capacitive coupling. In such designs, the respective gate materials are laid on planes parallel to the wafer surface. This type of topology would demand more surface area if higher coupling is needed [1,2]. To overcome this constraint, folding can be introduced in portions of the device to introduce area-saving vertical geometric features.

Fig. 1 shows a vertical section of a device configured to include a folded portion 10 to provide high capacitive coupling in a much smaller horizontal (i.e., chip) area than typical approaches. Layer 12 is recessed oxide (ROX) grown after forming a trench 14 by reactive ion etching. The floating polysilicon gate for charge storage is provided by doped polysilicon layer 16. The programming polysilicon gate 18 is formed by deposition over an intervening second oxide layer 20 and doped. In customary terminology, layer 20 is the "second gate" oxide. The usual "first gate" oxide 22 is formed after the trench oxide 12 is formed, and has a configuration similar to an FET gate. The second gate 20 structure has a major portion of its area contained in the trench 14 which is about 10 Mum deep [3]. Passivation insulation oxide 24 covers the device, except for metal interconnect 26.

Fig. 2 shows a horizontal section t...