Browse Prior Art Database

Short and Long ROS Patch

IP.com Disclosure Number: IPCOM000052939D
Original Publication Date: 1981-Aug-01
Included in the Prior Art Database: 2005-Feb-12
Document File: 3 page(s) / 58K

Publishing Venue

IBM

Related People

Trinh, H: AUTHOR

Abstract

Incorrect areas of read-only storage (ROS) or memory (ROM) are patched by bypassing directly to substitute memory or by also using software techniques, depending upon the size of the correction. The short patch employs combinational logic on address data to create an address to a patch memory, the content of which is acted upon as though it were data at the original address. The long patch employs the content of a patch memory along with software techniques to substitute patch memory for original memory in data processing routines.

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Short and Long ROS Patch

Incorrect areas of read-only storage (ROS) or memory (ROM) are patched by bypassing directly to substitute memory or by also using software techniques, depending upon the size of the correction.

The short patch employs combinational logic on address data to create an address to a patch memory, the content of which is acted upon as though it were data at the original address. The long patch employs the content of a patch memory along with software techniques to substitute patch memory for original memory in data processing routines.

Fig. 1 is a block diagram showing the added elements and controls to achieve the patch operation. The programmable logic array (PLA) 1 and the multiplexer (MUX) 3 may be conventional, readily available elements which function by combinational logic. The signal lines shown may be single or plural lines as convenient in standard circuit design. Where address bits enter the circuit, these are digital address bits from a standard data processing system operating with a ROS which is to be patched. The illustrated system employs sixteen bits of memory address. PLA 1 receives an input of address bits 4 through 15, the high-order address bits. PLA 1 also receives four bits constituting a page address, a page being a separate area of memory which is fully interrogated by address bits phi through 10. The new data for both the short patch and long patch is in a standard electrically programmable read-only memory (EPROM) 5.

Fig. 2 maps the content of EPROM 5, with the addresses being in conventional hexadecimal notation. Sixteen areas of sixteen bit bytes at locations phi phi phi H through phi F F H are programmed for the short patch operation, including the short patch sequence which is the initial entry into long patch, as will be described. The remainder of the EPROM at locations 1 phi phi H through 7 F F H are programmed for long patch operation. Each long patch area may be of variable length, with the end point defined by a jump instruction or the like in EPROM 5.

In operation, at a configuration of address bits 4 through 15, an area of central ROS to be corrected is defined. PLA 1 produces a signal on line SPEN, which is effective as a short patch enable control, and a four-bit translated address on the XLADR line. The translated address defines one of the sixteen short patch areas in EPROM 5. The SPEN signal passes 0R logic 7 to enable EPROM 5. Inverter 9 receives the signal and produces a signal on ROS Dis line which disables the central ROS.

The area of EPROM 5 addressed is then defined by the translated address bits 4 through 15 from PLA 1, which are passed by MUX 3, and by the direct lines ADR phi through 3, carrying the four low-order bits. One of the sixteen short patch entries in E...