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Stepped Oxide CCD With Asymmetrical Oxide Geometry

IP.com Disclosure Number: IPCOM000052940D
Original Publication Date: 1981-Aug-01
Included in the Prior Art Database: 2005-Feb-12
Document File: 5 page(s) / 173K

Publishing Venue

IBM

Related People

Alcorn, GE: AUTHOR [+3]

Abstract

A process is disclosed to fabricate stepped-oxide charge coupled device (CCD) electrodes which are asymmetrical in the direction of charge flow to improve charge transfer efficiency. A hardened photoresist mask technique is disclosed to form the stepped-oxide structure.

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Stepped Oxide CCD With Asymmetrical Oxide Geometry

A process is disclosed to fabricate stepped-oxide charge coupled device (CCD) electrodes which are asymmetrical in the direction of charge flow to improve charge transfer efficiency. A hardened photoresist mask technique is disclosed to form the stepped-oxide structure.

Charge coupled devices transport electric charge unidirectionally. The more enhanced the unidirectional charge flow is in a CCD design, the better is the charge transfer efficiency and speed of the device. Generally, the unidirectional flow of charge is achieved by applying to the cell electrodes trains of voltage pulses which are properly delayed with respect to one another. Still another approach employs unequal surface ion implantations to permanently form asymmetrical surface potentials along the charge flow direction. An alternate technique is disclosed herein for providing asymmetrical charge flow characteristics by forming stepped-oxide structures along the charge flow direction. The sequence of process steps is described in what follows with reference to the sequence of figures.

Mask #1. On a planar semiconductor substrate 1 (Fig. 1), grow a thick oxide layer 3 to about 5000 angstroms. Next, deposit a polysilicon N+ layer 4 to about 3000 angstroms. Coat layer 4 with a positive photoresist layer 6. Use mask #1 to form long parallel stripes of photoresist 6 which define the length of the thick oxide portion of the would-be stepped oxide electrode. After removing the exposed photoresist, bake the remaining photoresist at high temperature, so that it becomes insoluble during subsequent photoresist applications. This is a key step of the process. The technique of using the combination of a hardened photoresist mask and several other subsequent photoresist masks to obtain self- aligned windows is disclosed in U.S. Patent 4,201,800. At this stage of the process, the cross-sectional view is that shown in Fig. 1.

Mask #2. Deposit a second photoresist layer 8, and use plasma etching to define the openings in a second photoresist mask. The superposition of the openings in the first and second masks define windows 10 which leave exposed the polysilicon layer 4, as shown in Fig. 2. Fig. 3 shows the top view of the structure.

Reactive ion etch the portions of the polysilicon layer 4 exposed through windows 10 to form holes 12 of relatively steep sidewalls, as in Fig. 4. Dip etch in diluted hydrofluoric acid to enlarge holes 12 by laterally etching their steep oxide sidewalls 13.

As a result, polysilicon overhangs 14 are formed (Fig. 4). Remove masking layer 8 using conventional solvents.

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