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Shared Instruction Buffer for Multiple Instruction Streams

IP.com Disclosure Number: IPCOM000052946D
Original Publication Date: 1981-Aug-01
Included in the Prior Art Database: 2005-Feb-12
Document File: 3 page(s) / 74K

Publishing Venue

IBM

Related People

Blount, FT: AUTHOR [+3]

Abstract

When instruction buffers are added for contingent processing of alternative instruction streams, hardware cost and circuit delay are held to acceptable levels by partial sharing of buffer storage between instruction streams.

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Shared Instruction Buffer for Multiple Instruction Streams

When instruction buffers are added for contingent processing of alternative instruction streams, hardware cost and circuit delay are held to acceptable levels by partial sharing of buffer storage between instruction streams.

In a high-performance processor, an instruction buffer stores a limited number of consecutively-addressed instruction words. The buffer is loaded from storage one double-word at a time at double-word boundaries. Instructions are sequentially selected from the buffer one word at a time at half-word boundaries, since instruction sizes vary in half-word increments.

Another characteristic of a high-performance processor is pipelining and/or overlapping. While one instruction undergoes its second cycle of processing, the next sequential instruction undergoes its first cycle of processing.

Frequently, a branch instruction is encountered. Whether a branch is taken or not may not be determined for several cycles. Meanwhile, contingency processing of the branch-taken instruction stream cap be undertaken, so as not to delay such processing if the branch is in fact taken, especially for those branch instructions and/or conditions which have been statistically determined to have a greater probability of being taken than not. In order to provide for contingency processing of the alternate instruction stream, another instruction buffer is provided. As soon as it is determined whether or not the branch is taken, the unneeded instruction buffer is invalidated and can be used for another contingency instruction stream.

In the data processing system shown in U. S. Patent 4,200,927, three instruction buffers are provided, so that two successive branch instructions could start two additional instruction streams before the first branch instruction is executed and is determined to be a taken branch.

In this implementation, a first instruct...