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Conversion of PLA-Logic Implementations

IP.com Disclosure Number: IPCOM000052972D
Original Publication Date: 1981-Aug-01
Included in the Prior Art Database: 2005-Feb-12
Document File: 3 page(s) / 39K

Publishing Venue

IBM

Related People

Gilkinson, JL: AUTHOR [+2]

Abstract

A logic design in the form of a programmable logic array (PLA) is converted to equivalent random logic in a given target technology by representing the PLA as a set of technology-independent logic blocks, performing logic reductions, adding any required drivers and receivers, repowering outputs as required, and converting the technology-independent blocks to logic functions in the target technology.

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Conversion of PLA-Logic Implementations

A logic design in the form of a programmable logic array (PLA) is converted to equivalent random logic in a given target technology by representing the PLA as a set of technology-independent logic blocks, performing logic reductions, adding any required drivers and receivers, repowering outputs as required, and converting the technology-independent blocks to logic functions in the target technology.

The PLA format presents a relatively easy and structured method for designing logical functions. Although PLA implementations are dense in planar- wiring technologies, newer technologies permitting multilayer wiring can make more efficient use of silicon area with random-logic implementation. The problem then becomes one of converting a design in the FLA format to an implementation in an appropriate random-logic technology.

The first step in the conversion method transforms the PLA design into a set of technology-independent logic blocks. It is well known that a PLA can be represented as a two-level AND-OR logic net. Any extraneous, non-logical information is then removed. The logic is next transformed to a set of blocks which correspond to elementary functions in the ultimate implementation. For example, one technology might contain A,AI,AO and AOI functions (A=AND, O=OR, I=INVERT), whereas another might use O,OI,OA and OAI elements. Then, the resulting PLA description is expressed in the appropriate blocks with both output polarities available and with the assumption of potentially unlimited fanin and fanout.

The second step employs reduction techniques to remove redundant logic which may have been introduced in the preceding step. The drawing shows five of the many different algorithms which could be employed. Parallel reduction consolidates blocks which have the same inputs, such as E11-E12 and the same logic fun...