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Contact Sense Multiplexer for Long Line Use

IP.com Disclosure Number: IPCOM000052991D
Original Publication Date: 1981-Aug-01
Included in the Prior Art Database: 2005-Feb-12
Document File: 2 page(s) / 66K

Publishing Venue

IBM

Related People

Powell, KE: AUTHOR

Abstract

This arrangement monitors a plurality of alarm or like contact sense devices connected to a Central Processing Unit (CPU) over a single pair of voice-grade communication wire lines at minimal cost. A Time Division Multiplexing (TDM) circuit is utilized at a remote location to the system, and timing is controlled by a two-phase clocking circuit. The clocking circuit steps a counter which in turn provides binary address signals for operating the multiplexing circuit. When an alarm is noted, the pertinent address is transmitted to the TDM as a standard Dual Tone Multiple Frequency (DTMF) signal over a pair of voice-grade conductors. Thereafter, it is demodulated by a DTMF detector, and coupled to the DI or CI points of the CPU by an optocoupler device.

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Contact Sense Multiplexer for Long Line Use

This arrangement monitors a plurality of alarm or like contact sense devices connected to a Central Processing Unit (CPU) over a single pair of voice-grade communication wire lines at minimal cost. A Time Division Multiplexing (TDM) circuit is utilized at a remote location to the system, and timing is controlled by a two-phase clocking circuit. The clocking circuit steps a counter which in turn provides binary address signals for operating the multiplexing circuit. When an alarm is noted, the pertinent address is transmitted to the TDM as a standard Dual Tone Multiple Frequency (DTMF) signal over a pair of voice-grade conductors. Thereafter, it is demodulated by a DTMF detector, and coupled to the DI or CI points of the CPU by an optocoupler device. In addition to ten alarm inputs (1-10), two other inputs (0 and 11) are held high to provide check bits to the CPU to assure continuity of the system.

In operation, a contact closure at one of a number of alarm or sense points 10 (Fig. 1) applies a low level (ground, for example) potential to the TDM 12 (1 of 12) multiplexer. When this input port of the MUX 12 is addressed by the MAR (Memory Address Register) counter or register 18, the output of the MUX 12 will be the inverse of the input, and a high level will be applied to the AND gate 20.

The clock circuit 16 provides two timing signals T1 and T2. T1 is utilized to increment the MAR counter 18 or binary address register, and T2 provides gat...