Browse Prior Art Database

Linear Time Speedup of Fault Diagnosis in Array Processors

IP.com Disclosure Number: IPCOM000053027D
Original Publication Date: 1981-Aug-01
Included in the Prior Art Database: 2005-Feb-12
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Miranker, GS: AUTHOR

Abstract

A machine architecture, logic circuit, and test protocol is defined which allows identification of faulty processing elements (PEs) in an array processor in time proportional to processing element size not (PE size) x (no. of PEs).

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Linear Time Speedup of Fault Diagnosis in Array Processors

A machine architecture, logic circuit, and test protocol is defined which allows identification of faulty processing elements (PEs) in an array processor in time proportional to processing element size not (PE size) x (no. of PEs).

A technique that allows a linear time speedup in the identification of faulty processing elements in an array processor is outlined.

The identification of bad processing elements in array processors can be time consuming. Suppose that the bulk of the diagnostic tests for the full machine consists of repeating a sequence of test patterns in each PE of the array. It then becomes possible to run the tests in parallel in each of the PEs. If all of the processing elements are self-diagnosing, running the tests in parallel is easy to do. If they must be tested from a host, some additional architectural mechanism must be devised.

In order to run diagnostics simultaneously in all processor elements, we assume the machine has a single parallel bus over which test stimuli can be transmitted and test responses received. The bus must be a wire-ORed bus with signals asserted LOW. We also assume that broadcast writes to all PEs are allowed and broadcast reads are also implemented. (By broadcast read, it is meant that all array elements place their test responses on the bus at the same time.) Finally, each PE has a RESPONSE register which is bit-wise exclusive ORed with the data normally plac...