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Semiconductor Wafer Decelerator

IP.com Disclosure Number: IPCOM000053063D
Original Publication Date: 1981-Aug-01
Included in the Prior Art Database: 2005-Feb-12
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Beliveau, M: AUTHOR

Abstract

This article describes a retarding mechanism for decelerating sliding, fragile semiconductor wafers, which reduces or eliminates wafer breakage and chipping.

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Semiconductor Wafer Decelerator

This article describes a retarding mechanism for decelerating sliding, fragile semiconductor wafers, which reduces or eliminates wafer breakage and chipping.

Wafers 10 are often fed, under the force of gravity, such as a slide 11, onto various tool supports 12 where they can then be handled or otherwise treated. Presently, such wafers are stopped by impacting against rigid stops which can cause breakage or chipping of the edges of the device which can cause severe problems. The improved retarding mechanism 13, shown herein, consists of a center support strip 14 carrying at one end a double-ended, cantilever spring 15 which has its ends 16 bent to apply a retarding force upon the edges of the wafers being received by the support 12.

Strip 14 is mounted over the support 12 and further has a positive spring stop 17 attached to its end such that when the wafer 10 slides beneath the cantilever spring ends 16 where it is drastically slowed without sudden jarring or impacting, it finally rests against the positive spring stop 17. This cantilever spring mechanism can be mechanically actuated to permit the wafer 10 to be raised or otherwise removed from the unit after complete stoppage has been achieved. Breakage of wafers, using this spring-retarding mechanism, have been reduced 25%, thus achieving significant savings.

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