Browse Prior Art Database

Latch Check Circuit

IP.com Disclosure Number: IPCOM000053086D
Original Publication Date: 1981-Aug-01
Included in the Prior Art Database: 2005-Feb-12
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Dutton, PF: AUTHOR

Abstract

This arrangement provides a check that a plurality of latches have reset to their proper initial condition after a machine cycle. After a processor has been designed and all of the hardware has been put together, system debug begins. During this portion of the system development, all sorts of hardware and software problems are encountered. A particular group of these problems is the result of something that happened in time past.

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Latch Check Circuit

This arrangement provides a check that a plurality of latches have reset to their proper initial condition after a machine cycle. After a processor has been designed and all of the hardware has been put together, system debug begins. During this portion of the system development, all sorts of hardware and software problems are encountered. A particular group of these problems is the result of something that happened in time past.

For example assume that the central processing unit issues a storage word that results in a cache miss. This in turn invokes a hardware routine that reads in the correct page of data from the main memory to the cache. Now assume that at the end of this operation a control latch that should have been reset was not. The processor could then execute many operations before those same controls are needed again. When they are needed again, the hardware does not function properly. Often this results in the system hanging (no processing taking place), or it could be stuck in an endless micro-code loop. By this time a great amount of useful information contained in the state of the system, latches and arrays, has been lost. These are very difficult problems to troubleshoot and, as a result, consume a lot of time.

A circuit as shown in the drawing can be constructed that can examine the state of all latches after a hardware routine has completed and before the next one has started. If any latch is not in its reset state, a mach...