Browse Prior Art Database

Programmable Basic Storage Module Controls

IP.com Disclosure Number: IPCOM000053090D
Original Publication Date: 1981-Aug-01
Included in the Prior Art Database: 2005-Feb-12
Document File: 4 page(s) / 115K

Publishing Venue

IBM

Related People

Dutton, PF: AUTHOR [+2]

Abstract

It is not uncommon for the technology of a high-speed digital computer to be developed in parallel with the logic for the computer itself. This can create problems, especially where timing and sequencing of the logic are critical to the operation of, for example, a memory array. Every time the main storage array specifications (timing, etc.) are changed, the change must be absorbed by the controls hardware. In an LSI (large-scale integration) environment, this results in costly changes to chips. The present arrangement is utilized to alleviate such changes.

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Programmable Basic Storage Module Controls

It is not uncommon for the technology of a high-speed digital computer to be developed in parallel with the logic for the computer itself. This can create problems, especially where timing and sequencing of the logic are critical to the operation of, for example, a memory array. Every time the main storage array specifications (timing, etc.) are changed, the change must be absorbed by the controls hardware. In an LSI (large-scale integration) environment, this results in costly changes to chips. The present arrangement is utilized to alleviate such changes.

This improved control is used with an array in which the output bits map one- for-one to control lines (horizontal microcode). The "states" of these control lines, relative to time, can be stored as 1 for "active" and 0 for "inactive". A 1K by 9 array, for example, as shown in Fig. 1A, can drive up to 8 control lines, with one bit reserved for parity or an error correcting code. As additional control lines are required, more arrays can be added (while using the same addressing). Sections of the array (conceptually contiguous locations) are devoted, respectively, to different control sequences, as shown in Fig. 1C. Such control sequences are, of course, predefined, and would be loaded at power-on reset (POR). Data would be fetched (addressed) by a specially designed Address Generator circuit 3 capable of translating a hardware sequence "request" into a sequence of array addresses, supplied to the arrays 7. Such sequences can vary in length; therefore, it is appropriate to "feed back" a signal from the array outputs to the address generator on a line 9, indicating that the requested operation has been completed.

It should be noted that the "address generator" is designed to take advantage of unu...