Browse Prior Art Database

Attached Processors Data Copies

IP.com Disclosure Number: IPCOM000053094D
Original Publication Date: 1981-Aug-01
Included in the Prior Art Database: 2005-Feb-12
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Dutton, PF: AUTHOR [+2]

Abstract

In an attached processor system that utilizes two independent storage controllers, contention will exist for common data located in the caches. To reduce this contention, which reduces inpaging and outpaging of the data, copy bits are provided for each page in the cache. This bit, when on, indicates that the data could reside in each storage controller's cache.

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Attached Processors Data Copies

In an attached processor system that utilizes two independent storage controllers, contention will exist for common data located in the caches. To reduce this contention, which reduces inpaging and outpaging of the data, copy bits are provided for each page in the cache. This bit, when on, indicates that the data could reside in each storage controller's cache.

Copied data is essentially read only, and if an attempt is made to write into it from either processor, the opposite side's data is invalidated (Fig. 1).

The theory of operation of the arrangement shown in Fig. 1 and Fig. 2 is described below.

The Instruction Processor Unit (IPU) issues a storage command to its associated storage controller, and it is determined that the requested data is not present in its associated cache.

The storage controller requests the opposite storage controller to check its directory to see if the data is present there. If not there, the requesting storage controller will transfer it in from main storage.

If the data is present and it is not modified, the copy bits will be turned on in each directory and the data will be transferred to the requesting storage controller.

If either IPU attempts to write to this copy's data, the opposite side will invalidate that page.

This operation significantly raises the performance of an attached processor system, since most of the data in the cache will not be subject to change.

These copy bits can be in the cac...