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Browse Prior Art Database

Formation of Low Capacitance Diffusions

IP.com Disclosure Number: IPCOM000053103D
Original Publication Date: 1981-Aug-01
Included in the Prior Art Database: 2005-Feb-12
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

Dockerty, RC: AUTHOR

Abstract

Fig. 1 shows a N+ diffusion 10 in the conventional MOSFET (metal-oxide) semiconductor field-effect transistor) technology. The perimeter component of junction capacitance is high because the N+ diffusion intersects the P+ field junction isolation implant 11. Silicon dioxide-phosphosilicate glass layer 12 covers the device.

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Formation of Low Capacitance Diffusions

Fig. 1 shows a N+ diffusion 10 in the conventional MOSFET (metal-oxide) semiconductor field-effect transistor) technology. The perimeter component of junction capacitance is high because the N+ diffusion intersects the P+ field junction isolation implant 11. Silicon dioxide-phosphosilicate glass layer 12 covers the device.

Fig. 3 shows a low capacitance N+ diffusion 15 which can be made with no extra masks. Also shown is the substrate contact area 16. The structure of Fig. 3 is made by a conventional semi-recessed oxide silicon gate FET process up to the point where the source-drain regions are to be formed by implantation.

Prior to the source-drain ion implant a blockout resist mask 20 is formed, as shown in Fig. 2 to define the desired N+ regions to be made. The N+ source- drain ion implant forms the N+ regions 15. The resist is stripped. A thermal reoxidation and deposition of phosphosilicate glass 22 thereover completes the structure shown in Fig. 3.

The silicon dioxide and phosphosilicate glass layer 22 thickness over the substrate contact 16 is slightly less than the thickness over the N+ regions 15. Therefore, all contacts can be opened with one contact mask.

This process can be used with a semi-recessed oxide isolation or full recessed oxidation, single polycrystalline silicon or double polycrystalline silicon process. Figs. 2 and 3 illustrate the semi recessed isolation 25 with a P+ junction isolation region 26 the...