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Technique for making Substrate Contact from the Top Surface Using the Double Epitaxial Process

IP.com Disclosure Number: IPCOM000053106D
Original Publication Date: 1981-Aug-01
Included in the Prior Art Database: 2005-Feb-12
Document File: 2 page(s) / 66K

Publishing Venue

IBM

Related People

Abbas, SA: AUTHOR [+4]

Abstract

The substrate, which is preferably a low resistivity P+, can be electrically contacted at one or two places on each chip or can be a contact ring at the periphery of the chip. The process sequence is as follows: 1. Grow 4-5-micrometer P/-/ epitaxial layer 10 over the P+ substrate 9. 2. Form blanket N/+/ subcollector region 11 from the top in the P epitaxial layer 10. 3. Grow 1-micrometer N/-/ epitaxial layer 12 over this subcollector 11. 4. Thermally oxidize the surface of layer 12 to form silicon dioxide layer 13 of about 1000 A in thickness. 5. Deposit layer 14 of about 250 ;(##) of silicon nitride. 6. Deposit a layer 15 of about 1.5 micrometers low pressure chemically vapor deposited (CVD) silicon dioxide for the trench mask. 7. Using lithography techniques develop a contact mask pattern in layer 16. 8.

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Technique for making Substrate Contact from the Top Surface Using the Double Epitaxial Process

The substrate, which is preferably a low resistivity P+, can be electrically contacted at one or two places on each chip or can be a contact ring at the periphery of the chip. The process sequence is as follows: 1. Grow 4-5- micrometer P/-/ epitaxial layer 10 over the P+ substrate 9. 2. Form blanket N/+/ subcollector region 11 from the top in the P epitaxial layer 10. 3. Grow 1- micrometer N/-/ epitaxial layer 12 over this subcollector 11. 4. Thermally oxidize the surface of layer 12 to form silicon dioxide layer 13 of about 1000 A in thickness. 5. Deposit layer 14 of about 250 ;(##) of silicon nitride. 6. Deposit a layer 15 of about 1.5 micrometers low pressure chemically vapor deposited (CVD) silicon dioxide for the trench mask. 7. Using lithography techniques develop a contact mask pattern in layer 16. 8. Reactive ion etch (RIE) an opening in layers 15, 14 and 13 down to the silicon epi layer 12 using CF(4)/H(2) as the ambient to produce the Fig. 1 structure. 9. Strip the resist layer 16. 10. RIE the silicon layers 10, 11 and 12 to P(+) substrate 9 using layer 15. 11. Refill the trench with P-doped polysilicon 17, and planarize about half way into the silicon dioxide layer 15. 12. Strip the silicon dioxide layer 15 to the silicon nitride layer 14, over the rest of the wafer. 13. Form about 1000 Angstrom layer 18 of thermal SiO over the contact to produce the Fig. 2 s...