Browse Prior Art Database

High Density Multiplexed Polarity Hold Latch

IP.com Disclosure Number: IPCOM000053112D
Original Publication Date: 1981-Aug-01
Included in the Prior Art Database: 2005-Feb-12
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Sullivan, SC: AUTHOR [+2]

Abstract

This circuit combines an FET latch with a multiplexing function to reduce device count, power dissipation and wiring. As shown in the circuit schematic, three transfer gates make up a 3 out of 1 multiplexor. The outlined portion is a standard polarity hold latch. The logic diagram depicts how the control signals are produced. The master clock pulse is ANDed with a select line to enable one of three transfer gates. There could be any number of transfer gates added for any size multiplexor required. The NOR of the clock lines provides timing for the latch itself. With the use of some logic done in the powering up circuits, and the elimination of two devices previously needed, a denser circuit can be obtained with only four control lines and eight devices. In large registers, significant chip area savings can be realized.

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High Density Multiplexed Polarity Hold Latch

This circuit combines an FET latch with a multiplexing function to reduce device count, power dissipation and wiring. As shown in the circuit schematic, three transfer gates make up a 3 out of 1 multiplexor. The outlined portion is a standard polarity hold latch. The logic diagram depicts how the control signals are produced. The master clock pulse is ANDed with a select line to enable one of three transfer gates. There could be any number of transfer gates added for any size multiplexor required. The NOR of the clock lines provides timing for the latch itself. With the use of some logic done in the powering up circuits, and the elimination of two devices previously needed, a denser circuit can be obtained with only four control lines and eight devices. In large registers, significant chip area savings can be realized.

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