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Conditional Return Micro/ Instruction

IP.com Disclosure Number: IPCOM000053145D
Original Publication Date: 1981-Sep-01
Included in the Prior Art Database: 2005-Feb-12
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Kiselak, JA: AUTHOR [+2]

Abstract

Disclosed is a microinstruction that will save microcode words in a routine that contains a number of tests, all of which branch to the same exit.

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Conditional Return Micro/ Instruction

Disclosed is a microinstruction that will save microcode words in a routine that contains a number of tests, all of which branch to the same exit.

In some microcode routines it is necessary to do a series of tests before actual execution of the instruction, or function, can be done. If any of the tests are failed, execution of the instruction will be terminated.

Fig. 1 is illustrative of this type of routine. Here, now all execution involves successive execution of microcode control words A, B, C(0), D, E(0), F(l), G, H. Three tests are specified (at A, C(0), and D), and the results of these tests are used in the branches at words B, D, E(0), respectively. As Fig. 1 shows, if the result of TEST1 is ONE, or TEST2 is ONE, or TEST3 is ZERO, then execution is terminated. Each time such a test is made, the microcode branch requires two words. One is a useful word (C(0), E(0), F(1)), and the other may serve no other purpose than to point to an exit. If, as sometimes happens, many tests point to the same exit, then words like C(1), E(1) and F(0) are all identical. They may account for 10% or more of the words in a microcode routine.

A new instruction can "free up" words like C(1), E(1), and P(0) by a variation on the microcode LINK/RETURN mechanism. Such mechanisms today allow a microorder to set up an address (via a LINK microorder) and later branch to that address (via a RETURN microorder). This article proposes a conditional return (CRTN) order. The order w...