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Browse Prior Art Database

Instruction Fetch

IP.com Disclosure Number: IPCOM000053147D
Original Publication Date: 1981-Sep-01
Included in the Prior Art Database: 2005-Feb-12
Document File: 2 page(s) / 13K

Publishing Venue

IBM

Related People

Hughes, JF: AUTHOR [+6]

Abstract

The processor described in U. S. Patent 4,200,927 has the following mechanism to handle branches and instruction fetches: - Operand fetch requests, both from the decoder (IPPF) and the E-unit, have priority over an instruction fetch (I-fetch) request. - There are three instruction buffers, each four doublewords deep, and they contend for I-fetching according to a Least Recently Used (LRU) algorithm. - Following the decode of a conditional branch, the I-unit continues decoding instructions, in conditional mode, according to the guess as to the branch outcome (BC and BCR are predicted to fall through; BXLE, BXL, BCT and BCTR to be taken). - When the branch is resolved by the E-unit, only the I-buffer containing the correct branch path is kept, and the other I-buffer is released.

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Instruction Fetch

The processor described in U. S. Patent 4,200,927 has the following mechanism to handle branches and instruction fetches: - Operand fetch requests, both from the decoder (IPPF) and the E-unit, have priority over an instruction fetch (I-fetch) request. - There are three instruction buffers, each four doublewords deep, and they contend for I-fetching according to a Least Recently Used (LRU) algorithm. - Following the decode of a conditional branch, the I-unit continues decoding instructions, in conditional mode, according to the guess as to the branch outcome (BC and BCR are predicted to fall through; BXLE, BXL, BCT and BCTR to be taken). - When the branch is resolved by the E-unit, only the I-buffer containing the correct branch path is kept, and the other I-buffer is released. Depending on the correctness of the branch guess, the instructions conditionally decoded are processed by the E-unit or purged. - The three I- buffers allow a second conditional branch to be conditionally decoded, before a first one is resolved. - Following the decoding of a branch, the first doubleword of the target is fetched with operand fetch priority (hence, the request for the first doubleword of the target does not compete as an instruction fetch).

The I-buffers are often empty when instructions are needed. This is due to the low priority of I-fetches and the contention between the three I-buffers. When a conditional branch is decoded, instructions are fetched along both the target path and the fall through path. Since the cache bus utilization for operand requests is already high, there are not enough free slots to prime both the target and the fail through I-buffers. Improvement in processor performance can be achieved if only one I-buffer requests instructions from the cache. The I-buffer given priority is the one assigned to contain ins...