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Data Transfer Via a One-Byte Interface between a Service Processor and a Central Processor

IP.com Disclosure Number: IPCOM000053148D
Original Publication Date: 1981-Sep-01
Included in the Prior Art Database: 2005-Feb-12
Document File: 2 page(s) / 14K

Publishing Venue

IBM

Related People

Kahng, SS: AUTHOR [+3]

Abstract

A simplified system design eliminates a separate bus and port to storage for a Service Processor (SP). A new port for the Service Processor is provided through the Central Processor (CP). A hardware microcode interface permits transfer of data between two systems utilizing a fast one-byte data transfer mode utilizing the PSW (Program Status Word) Wait bit, avoiding the delays of an interrupt and its reset on both sides of the interface.

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Data Transfer Via a One-Byte Interface between a Service Processor and a Central Processor

A simplified system design eliminates a separate bus and port to storage for a Service Processor (SP). A new port for the Service Processor is provided through the Central Processor (CP). A hardware microcode interface permits transfer of data between two systems utilizing a fast one-byte data transfer mode utilizing the PSW (Program Status Word) Wait bit, avoiding the delays of an interrupt and its reset on both sides of the interface.

The hardware interface between a SP and a CP consists of a 16-bit Q Bus that can be written and read. The definition of the CP bus bits are: Bit 0 - PSW Wait Bit Bit 1 - Manual Loop Bit Bits 2-7 - Not Assigned Bits 8-15 - Data (Bits 24- 31 of B-Register in CP) The CP cannot read bits 0-7.

The following general conditions apply to all of the data transfer commands.
1. All addresses are expected to be absolute and on specified boundaries. If the boundary requirements are not followed, the results will be unpredictable. 2. Even though not every command will use all of the data, the CP expects 7 bytes of initial data at the start of each command (1-byte command, 4-byte address, 2- byte data length count). 3. Data length count is expected to use zero origin (i.e., a length of 3 would have a count of 2). The length count must be a multiple of the boundary requirement minus 1. 4. Once a data transfer is started, the requested number of bytes must be transferred. Data From CP To SP

Following is the general sequence of steps involved in transferring data from the CP to the SP.

1. SP, via the Q bus, writes the following 7 bytes of data to the CP. 1-byte command 4-byte address 2-byte data length count 2. CP decodes the command and reads and assembles the address and count data in logical store as the SP sends the 7 bytes across the CP/SP Q bus. 3. CP saves the PSW Wait bit in local store. During the transfer operation to the SP, the Wait bit is used as a data valid line. 4. CP fetches the first byte of data into the B(24:31) register for later transfer to Q bus. The SP is interrupted by a microorder. 5. SP reads the first byte of data, resets the interrupt from CP, and does a Write Q to CP. 6. CP looks for reset of interrupt and then for a Write Q signal from SP. At this point the CP and SP go into a fa...