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Trigger/Latch Technique for Hardware Simulation Programs

IP.com Disclosure Number: IPCOM000053150D
Original Publication Date: 1981-Sep-01
Included in the Prior Art Database: 2005-Feb-12
Document File: 3 page(s) / 51K

Publishing Venue

IBM

Related People

Anderson, DW: AUTHOR [+3]

Abstract

Introduction. The trigger/latch technique is a convenient technique for handling a difficult simulation job: the modelling of simultaneous activities on a digital computer which is by nature a sequential device

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Trigger/Latch Technique for Hardware Simulation Programs

Introduction

The trigger/latch technique is a convenient technique for handling a difficult simulation job: the modelling of simultaneous activities on a digital computer which is by nature a sequential device.

Description of the Trigger/Latch Technique

Every facility in the modelled hardware mechanism (adders, control registers, queue registers, bus "slots", etc.) is represented in two states: a trigger and a latch. The trigger is the prior-cycle, or "used-to-be" state. The latch is the incipient or "about-to-be" state. By testing the value of corresponding triggers and latches, the simulator can tell where it has been and where it is going. The triggers represent the very recent past, but as history, they may not be tampered with. The latches are present-future and may be altered. The use of the trigger/latch technique is governed by this cardinal rule: test triggers; set latches.

At the end of each simulated machine cycle an "update" function increments the modelled processor clock and copies the contents of all latches into their corresponding triggers. This is done unconditionally, despite the fact that in many cases the trigger and latch are already identical in value.

ln actual hardware, there may be several mechanisms contending for the same shared resource. A predefined priority scheme dictates which mechanism prevails, with the others forced to endure a delay, and make the same request on a subsequent cycle. It is this kind of "race condition" which is one of the vexing problems in the task of hardware simulation. The value of the trigger/latch technique is that it simplifies this problem.

An Illustrative Example

Suppose that some part of the hardware to be simulated resembles an ordinary two-color traffic light. Postulate that one part of the modelled hardware performs Process A while another part of the hardware performs Process B. As both processes are performed simultaneously, they may be viewed in parallel, as shown in Fig. 1.

The result of these two processes performed simultaneously is that whatever the color of the light b...