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Browse Prior Art Database

Scatter Gather Buffering of Synchronous Serial Data

IP.com Disclosure Number: IPCOM000053176D
Original Publication Date: 1981-Sep-01
Included in the Prior Art Database: 2005-Feb-12
Document File: 3 page(s) / 45K

Publishing Venue

IBM

Related People

Eiselen, ET: AUTHOR

Abstract

This invention relates to a method and apparatus for scattering r segments of a bit string obtained from one of m serial binary sources among r of n buffers and for gathering said r segments from said r buffers for recording in one of m sinks. The method steps include (1) parallel coupling r buffers to the source/ sink, (2) broadcast transmitting the bit string, and (3) electronically gating each of the r buffers on a byte count basis to secure transfer thereto of counterpart segments of the string. Apparatus for practicing the method includes a cross-point switch whose rows terminate source/sinks and whose columns terminate counterpart buffers. Multiple buffers can be lacked to a single row by centrally settable switches.

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Scatter Gather Buffering of Synchronous Serial Data

This invention relates to a method and apparatus for scattering r segments of a bit string obtained from one of m serial binary sources among r of n buffers and for gathering said r segments from said r buffers for recording in one of m sinks. The method steps include (1) parallel coupling r buffers to the source/ sink, (2) broadcast transmitting the bit string, and (3) electronically gating each of the r buffers on a byte count basis to secure transfer thereto of counterpart segments of the string. Apparatus for practicing the method includes a cross- point switch whose rows terminate source/sinks and whose columns terminate counterpart buffers. Multiple buffers can be lacked to a single row by centrally settable switches.

The data transfer is set up by a microprocessor. It decides which memory units are to be involved in the data transfer, based on resource allocation algorithms appropriate to the control unit in which this invention is used. The resource management algorithm is not a part of this article. The microprocessor sets bits in the cross-point control register to make the necessary connections between the device and the selected memory units. It loads the control registers in each memory unit involved in the data transfer to control the portion of the data record to be transferred to/from that memory unit, Then the microprocessor enables the data transfer.

Fig. 1 shows an external device or channel connected through an illustrative cross-point switch to a typical memory unit. The vertical lines in the cross-point switch go to the memory unit, and the horizontal lines go to the device or channel adapter. Both the data path and the clocking path are shown. The clock signal always flows from the device, or channel, toward the memory. The point where a connection is made is shown by a diagonal line.

Each memory unit installed in the control unit would appear the same as the one shown in Fig. 2. The memory element has a bidirectional data path and typical control lines. The control logic necessary to transfer the proper portion of the data record to this memory unit is shown in detail.

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