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Browse Prior Art Database

ECL Circuit Adaptable to Delay Control

IP.com Disclosure Number: IPCOM000053186D
Original Publication Date: 1981-Sep-01
Included in the Prior Art Database: 2005-Feb-12
Document File: 3 page(s) / 63K

Publishing Venue

IBM

Related People

Christopherson, WA: AUTHOR

Abstract

This circuit arrangement minimizes chip-to-chip circuit speed differences by determining the delay of a given chip and regulating the electric power supplied to that chip. The delay time is sensed and correcting potential is developed and applied to the logic circuits by a delay regulator.

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ECL Circuit Adaptable to Delay Control

This circuit arrangement minimizes chip-to-chip circuit speed differences by determining the delay of a given chip and regulating the electric power supplied to that chip. The delay time is sensed and correcting potential is developed and applied to the logic circuits by a delay regulator.

Fig. 1 depicts an example 10 of logic circuitry to be subjected to delay regulation. The delay regulator consists of a phase comparator 12, a frequency- to-potential converter 14, a voltage CS (current source) generator 16, and a voltage-controlled oscillator (VCO) circuit 18. The phase compare circuitry 12 compares the off-chip clock signal to the VCO signal. The outputs U and D create a signal that has a pulse width directly proportional to the phase difference of the input clock signal and the VCO signal. This pulse-width sensitive signal has the same frequency as the input clock signal.

The signals U and D go to the frequency-to-voltage converter 14 which removes this carrier input clock frequency from the signal. The V(cs) generator 16 signal controls the power in the circuitry 10 which may comprise logic gates, for example, on the chip. In this particular example, the V(cs) generator 16 controls the current in the current source 22 of the logic gate 10. Increasing V(cs) increases the power in the gate 10 and the other gates (not shown), whereas decreasing V(cs) decreases the power in the gates.

The VCO 18 produces a signal whose frequency is proportional to the input V(cs) signal. The VCO circuit is composed of the same type logic gates as on the remaining part of the chip. The gates in the VCO are connected in a feedback loop so as to oscillate. Thus, as the V(cs) signal affects the gate delay of the logic gate, it also changes the frequency-to-potential converter, and the VCO creates a phase-locked loop.

By using this phase-locked loop technique, the VCO will lock onto the input clock signal. Lock is a term used here to indicate that the native frequency is essentially the same as the reference frequency. This phase-locked loop action will reject process, temperature, and power supply changes within the ability of the VCO to lock onto the clock. Once the VCO has locked, the power to the remaining logic gates on the chip has changed so that the gate delay now becomes controlled by the input clock frequency signal. The input clock signal, which now at the system level goes to all chips, controls the gate delay on each individual chip, regardless of the power the logic gate dissipates, the temperature of the chip, or the lot-to-lot process changes that occur during the manufacturing of the chip. The only circuitry required on the chip is the VCO, which senses the speed or gauge delay which exists on the chip.

Fig. 1 depicts exemplary emitter coupled logic (ECL) circuit 10 proposed as suitable for delay control. This same logic circuit 20 is arranged to form the VCO
18. The current source T(cs), R...