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Processor Control Using Cycle Types

IP.com Disclosure Number: IPCOM000059608D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 3 page(s) / 78K

Publishing Venue

IBM

Related People

Finney, DW: AUTHOR

Abstract

This article describes a processor control technique utilizing cycle types to keep all subunits of the CPU synchronized. In a pipelined processor with total hardware control, the processor logic can be partitioned in several chips by functions so that each chip requires different control lines to be generated, as illustrated in block diagram in Fig. 1 which shows the processor and storage management unit. In order to minimize the amount of wiring between chips and the number of drivers and receivers required, which causes excessive logic delays and degrades overall processor performance, the next instruction is loaded into a set of control registers in each chip. These control registers are illustrated in Fig. 2 for the control chip.

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Processor Control Using Cycle Types

This article describes a processor control technique utilizing cycle types to keep all subunits of the CPU synchronized. In a pipelined processor with total hardware control, the processor logic can be partitioned in several chips by functions so that each chip requires different control lines to be generated, as illustrated in block diagram in Fig. 1 which shows the processor and storage management unit. In order to minimize the amount of wiring between chips and the number of drivers and receivers required, which causes excessive logic delays and degrades overall processor performance, the next instruction is loaded into a set of control registers in each chip. These control registers are illustrated in Fig. 2 for the control chip. Each chip generates all control signals required on the chip directly from decodes of these control registers. However, there are several external conditions which may occur, such as power-on re set, interrupts, cache miss, etc., which must be handled.

To ensure that all chips keep the control registers synchronized at all times, the control chip generates a three-bit encoded cycle type which is distributed to all the chips to control the control registers. Fig. 3 illustrates the timing relationships of the control registers. The following is a description of the cycle types and the actions taken in that cycle. 000 Normal Cycle - All four instructions in the pipe are simultaneously being worked on in their respective phase. OE All instruction address registers (IARs) and control registers are clocked. OE The control valid bits are propagated to the next control register. 011 General-purpose register (GPR) read extended cycle - This cycle is used to do initial setup for the next instruction to be executed. OE The execute cycle A and B control registers are not clocked. OE The write cycle A control register is set invalid. OE The previous result is written to the GPR, Save Restore Register (SRR) 0, SRR1 or Machine State Register (MSR), as required. OE The Channel Address Register (CAR) and IARs are not clocked. OE No instruction fetch is initiated. OE

This cycle type is used to allow the condition met and address generation logic of branches and traps to sequence properly. 010 Execute extended cycle - Only the instruction in the execute phase is active during this cycle. OE Control registers are not clocked. OE

No IARs are clocked. OE No program accessible registers Condition (COND), Multiply/Quotent (MQ), MSR, SRR0, SRR1, or GPRS or internal working registers: namely, register B output, register A output, B register or Z registers which are clocked (not shown). OE For loads and stores, the CAR is loaded, and the storage request is initiated. OE For update and load, the GPR (RA) is written with the updated ADDR and, if the next instruction uses this GPR, the data is gated to the RA output and the...