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Raster Refresh Compression Data Structure Enhancement

IP.com Disclosure Number: IPCOM000059610D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Edgar, AD: AUTHOR [+3]

Abstract

The present method increases the processor's available memory by adding a successive run length instruction to the instruction set of the data compression algorithm for bit map controlled all-points-addressable (APA) displays. The successive run length instruction instructs the raster refresh controller to continue the shifting operation on the previously defined data word, and thus allows a data word to be followed by several instruction words. Using the present method, fewer words are required in the bit map memory. This reduces the memory required for the bit map and reduces the contention between the computer and the raster refresh controller, and thus improves the system performance.

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Raster Refresh Compression Data Structure Enhancement

The present method increases the processor's available memory by adding a successive run length instruction to the instruction set of the data compression algorithm for bit map controlled all-points-addressable (APA) displays. The successive run length instruction instructs the raster refresh controller to continue the shifting operation on the previously defined data word, and thus allows a data word to be followed by several instruction words. Using the present method, fewer words are required in the bit map memory. This reduces the memory required for the bit map and reduces the contention between the computer and the raster refresh controller, and thus improves the system performance. Additionally, a data word containing the value of the previous data word's low- order bit no longer has to be implanted in the bit map memory for data changes, which minimizes the complexity for organizing and modifying the bit map memory and gives the computer more time to perform other functions. A functional description of a successive run length instruction implementation is shown in the figure. Without the successive run length instruction, the run length counter's load S/R signal would input the data shift register's mode control input directly. Thus, the data shift register would load every time the run length counter reached the end of its run length. With the successive run length instruction integrated into the shif...