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Multi-Write/Single-Read Memory Access Scheme for Common Data Base Multiprocessor System

IP.com Disclosure Number: IPCOM000059611D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 3 page(s) / 60K

Publishing Venue

IBM

Related People

Chang, LL: AUTHOR [+4]

Abstract

This article describes a multi-write/single-read (MWSR) memory access technique for a common data base multiprocessor system which increases the accessibility of the common data base. In a conventional common data base multiprocessor system, the address and data buses connected to the common data base are controlled by a bus arbiter so that the bus contention problem can be avoided. This method of avoiding bus contention reduces the accessibility of the data base a great deal. If more than one processor needs to access the data base, only one of them will be granted the control. All the rest have to wait until the selected processor finishes its operation. The MWSR memory access scheme disclosed herein is devised to increase the efficiency of the common data base accessibility in a multiprocessor system.

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Multi-Write/Single-Read Memory Access Scheme for Common Data Base Multiprocessor System

This article describes a multi-write/single-read (MWSR) memory access technique for a common data base multiprocessor system which increases the accessibility of the common data base. In a conventional common data base multiprocessor system, the address and data buses connected to the common data base are controlled by a bus arbiter so that the bus contention problem can be avoided. This method of avoiding bus contention reduces the accessibility of the data base a great deal. If more than one processor needs to access the data base, only one of them will be granted the control. All the rest have to wait until the selected processor finishes its operation. The MWSR memory access scheme disclosed herein is devised to increase the efficiency of the common data base accessibility in a multiprocessor system. The main advantage of this MWSR memory access scheme lies in the common data base read operation. Each processor can read its own data base copy independently when no data base updating is taking place. Thus, the hold-up time for each processor during the data base read operation is reduced to a minimum (only data base updating can hold it up). In a multiprocessor common data base system, there are more data base read operations than data base write operations. Therefore, the accessibility of the data base in a multiprocessor system will be increased considerably by using the MWSR memory access scheme. Referring to the drawing, all the processors 1 in this multiprocessor system have their own copies of the common data base memory 2. Any one of the processors can update all the copies, but only one can do it at any given time. Every one of the processors can read its own copy without bothering the other processors as long as none of the other processors is doing the updating. In case of updating, the processor(s) asking to update the common data base copies needs to issue a write request (WR) signal to write grant (WG) circuit 3. The WG circuit is just like a conventional bus arbiter which decides which processor controls the bus. Each processor receiv...