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Dual-Port Queue for Dual-Processor Systems

IP.com Disclosure Number: IPCOM000059613D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Chang, LL: AUTHOR [+4]

Abstract

This article describes an arrangement for increasing the usability of the communication area in a dual-processor system without causing any bus arbitration problem. In a conventional dual-processor system, the communication area for information exchange between two processors usually causes bus contention problems. The mostly-used method to avoid this problem is using a bus arbiter to control the access of this communication area. The basic bus arbitration principle is that only one processor is allowed to access this area at any time. If more processors than one need to access this area, only one of them is to be granted the control; the other one has to wait until the selected processor finishes its task. Processor's processing time is wasted during the waiting period.

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Dual-Port Queue for Dual-Processor Systems

This article describes an arrangement for increasing the usability of the communication area in a dual-processor system without causing any bus arbitration problem. In a conventional dual-processor system, the communication area for information exchange between two processors usually causes bus contention problems. The mostly-used method to avoid this problem is using a bus arbiter to control the access of this communication area. The basic bus arbitration principle is that only one processor is allowed to access this area at any time. If more processors than one need to access this area, only one of them is to be granted the control; the other one has to wait until the selected processor finishes its task. Processor's processing time is wasted during the waiting period. This dual-port queue (DPQ) structure is designed for increasing the usability of the communication area in a dual-processor system without causing any bus arbitration problem. Referring to the drawing, the DPQ described herein utilizes two M by N (size of the memory port is depending upon the application) memory ports 1 and 2 which can be accessed by either processor I or II. Each processor has two separate sets of "tri-stateable" address bus elements 3 and "tri-stateable" bidirectional data bus elements 4. Each set of buses is connected to one of the two separate memory ports. Each processor also has a set of port status bits which gives the information...