Browse Prior Art Database

AC TEST Performance in a DC Functional Tester

IP.com Disclosure Number: IPCOM000059629D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Desrosiers, B: AUTHOR [+4]

Abstract

This article relates to the design of an AC card which is supplied by external generators and tester signals to provide synchronized AC clocks to a unit to be tested. This allows AC test to be performed on a DC tester. The unit to be tested is a floating-point processor making use of two different clocks, namely, BUS CLOCKS which control all input/output communication interfaces of the unit and SYSTEM CLOCKS which control all transfers using only internal paths of the unit. The unit is tested at real speed on a standard DC tester by applying the BUS and SYSTEM CLOCKS in a synchronous manner. The card designed for this purpose is supplied by two external pulse generators and two tester signals.

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AC TEST Performance in a DC Functional Tester

This article relates to the design of an AC card which is supplied by external generators and tester signals to provide synchronized AC clocks to a unit to be tested. This allows AC test to be performed on a DC tester. The unit to be tested is a floating-point processor making use of two different clocks, namely, BUS CLOCKS which control all input/output communication interfaces of the unit and SYSTEM CLOCKS which control all transfers using only internal paths of the unit. The unit is tested at real speed on a standard DC tester by applying the BUS and SYSTEM CLOCKS in a synchronous manner. The card designed for this purpose is supplied by two external pulse generators and two tester signals. The frequency of the BUS CLOCKS is controlled by the tester (slow speed), while the frequency of the SYSTEM CLOCKS is tuned via an AC generator in order to perform all the internal transfers at real speed. Both BUS and SYSTEM CLOCKS are continuously applied to the unit which is designed to use the proper clocks depending upon the execution cycle. The clocks are produced at AC speed with the required delay and width. As shown in Fig. 1, generator C supplies the circuits in part C and synchronizes the generator in part B, the delay of which is variable. The NAND outputs CK C and CK B provide the SYSTEM CLOCKS, and the NAND outputs CK R and CK S provide the BUS CLOCKS. The operation of the circuits in part C is as follows: As shown...