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Interprocessor Command System Supporting Complex Commands

IP.com Disclosure Number: IPCOM000059633D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Cavill, BR: AUTHOR [+3]

Abstract

A technique is described whereby command information used in communication between a controlling microprocessor and a slave microprocessor is passed in a byte-wide parallel configuration using the same algorithm for simple and complex commands. Communication between a controlling and a slave microprocessor typically is performed in one of three ways. For simple operations, a single byte is passed between microprocessors and decoded similarly to a hardware logic decoder controlling an operation. For complex operations, communications are performed by sending commands which consist of a fixed number of multiple bytes in which each byte or frame contains a fixed set of information. However, this method requires extensive processor overhead in order to communicate simple functions.

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Interprocessor Command System Supporting Complex Commands

A technique is described whereby command information used in communication between a controlling microprocessor and a slave microprocessor is passed in a byte-wide parallel configuration using the same algorithm for simple and complex commands. Communication between a controlling and a slave microprocessor typically is performed in one of three ways. For simple operations, a single byte is passed between microprocessors and decoded similarly to a hardware logic decoder controlling an operation. For complex operations, communications are performed by sending commands which consist of a fixed number of multiple bytes in which each byte or frame contains a fixed set of information. However, this method requires extensive processor overhead in order to communicate simple functions. A third method is to use coding, similar to ASCII, in which some of the defined code combinations are reserved for control commands. The technique described herein and shown in Fig. 1 uses the basic hardware typically required for passing single command bytes between two microprocessors. This hardware includes two sets of eight-bit latches, namely, data latch 10 containing commands received from the controlling microprocessor and data latch 12 containing status to be returned from the slave microprocessor 16. The controlling microprocessor (not shown) places a byte in the command data latches 10 via inter-processor bus 11. This action also sets a latch 14, causing an interrupt to the slave microprocessor 16 which then reads the command data, resetting the interrupt latch 14. The slave microprocessor 16 sends status information back to the controlling microprocessor in an analogous manner via status data latches 12 and status interrupt latch 15. Each command can consist of one to eight bytes. Slave microprocessor 16 has the ability to respond that each byte was received....