Browse Prior Art Database

I2L Memory Cell

IP.com Disclosure Number: IPCOM000059643D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Knepper, RW: AUTHOR [+2]

Abstract

An I2L memory cell, shown in Fig. 1, has two performance limitations: (1) the sensing signal is relatively weak, and (2) cell stability is sensitive to bit line offset. There have been various proposals to overcome these conditions, one of which is shown in Fig. 2. TA, TB serve as read/write devices and operate in the normal mode during select. The normal current gain of TA and TB determines the speed of read/write operations. If b is small, read is slow and write is fast. If b is large, read is fast and write is slow. b can be adjusted by emitter-junction depth and dopant concentration. An I2L cell can be implanted with the integrated device of Figs. 3, 4 and 5. The advantage over the Fig. 2 cell is that a common process may be employed for both memory and logic.

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I2L Memory Cell

An I2L memory cell, shown in Fig. 1, has two performance limitations: (1) the sensing signal is relatively weak, and (2) cell stability is sensitive to bit line offset. There have been various proposals to overcome these conditions, one of which is shown in Fig. 2. TA, TB serve as read/write devices and operate in the normal mode during select. The normal current gain of TA and TB determines the speed of read/write operations. If b is small, read is slow and write is fast. If b is large, read is fast and write is slow. b can be adjusted by emitter-junction depth and dopant concentration. An I2L cell can be implanted with the integrated device of Figs. 3, 4 and 5. The advantage over the Fig. 2 cell is that a common process may be employed for both memory and logic. This allows convenient mix of memory and logic on the same chip. The circuit of the I2L memory cell is shown in Fig. 3. A cell layout is illustrated in Figs. 4 and 5. The PNP load Tx's, the inverted NPN Tx's and the SBD's (Schottky barrier diodes) are all integrated in a common N+ bed, which serves as a drain line. Fig. 6 illustrates a layout where one injector is shared by four NPN Tx's. There are many other possible layout schemes. The operation of the I2L memory cells is outlined in Fig. 7. During standby, bit lines are biased so that the read/write diodes are off. During selection, voltage levels for SL and DL are raised and (VSL-VDL) is increased slightly to raise the injection curr...