Browse Prior Art Database

Capacitive Load FET Static RAM in Trench Technology

IP.com Disclosure Number: IPCOM000059650D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Wang, W: AUTHOR

Abstract

A capacitive load field-effect transistor (FET) static random-access memory (RAM) in isolation trench technology is made less sensitive to a-particle disturbance during standby by the use of a trench sidewall capacitor determined by diffusion depth contiguous to the sides of the sidewalls. Six devices comprising a resistive load FET static RAM or a four- device quasi-static RAM (without resistive load) are very sensitive to a-particle disturbance during standby condition. This is due to the small standby current (in the nanoampere range) in the resistive load static RAM case, or the absence of current in the quasi-static RAM case. A capacitive load FET static RAM in trench technology provides fast read/write operation and eliminates a-particle sensitivity when provided with the trench sidewall capacitor C1 shown in the figure.

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Capacitive Load FET Static RAM in Trench Technology

A capacitive load field-effect transistor (FET) static random-access memory (RAM) in isolation trench technology is made less sensitive to a-particle disturbance during standby by the use of a trench sidewall capacitor determined by diffusion depth contiguous to the sides of the sidewalls. Six devices comprising a resistive load FET static RAM or a four- device quasi-static RAM (without resistive load) are very sensitive to a-particle disturbance during standby condition. This is due to the small standby current (in the nanoampere range) in the resistive load static RAM case, or the absence of current in the quasi-static RAM case. A capacitive load FET static RAM in trench technology provides fast read/write operation and eliminates a-particle sensitivity when provided with the trench sidewall capacitor C1 shown in the figure. The capacitance value is determined by the depth of the N-well diffusion which provides one of the electrodes of the capacitor. The oxide on the sidewalls of the trench provides the dielectric layer of the capacitor. The second electrode is formed by the doped (N+ or P+) polysilicon-filled trench. An optional thin oxide surface capacitor C2 can be connected in parallel with the sidewall capacitor C2 by forming the surface polysilicon layer and connecting it (not shown) to the trench polysilicon.

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