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Resistive-Coupled, Bipolar, Static RAM Cell

IP.com Disclosure Number: IPCOM000059652D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Chang, AY: AUTHOR [+3]

Abstract

An improved, integrated semiconductor circuit bipolar random-access memory (RAM) cell is described where each half of the cell employs a transistor with an intrinsic base resistor to act as the load. The geometric arrangement in the semiconductor is used to connect this load to the active transistor of the half cell. This is in contrast with the normal approach where a separate resistor region is used as the load. Fig. 1 shows a typical circuit employing the new configuration. The circuit is similar to those commonly used as a RAM cell. Node 34 would normally be a bit line connection of a memory array, with node 35 being the complementary bit line connection. Transistor 2 is the output device for node 34.

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Resistive-Coupled, Bipolar, Static RAM Cell

An improved, integrated semiconductor circuit bipolar random-access memory (RAM) cell is described where each half of the cell employs a transistor with an intrinsic base resistor to act as the load. The geometric arrangement in the semiconductor is used to connect this load to the active transistor of the half cell. This is in contrast with the normal approach where a separate resistor region is used as the load. Fig. 1 shows a typical circuit employing the new configuration. The circuit is similar to those commonly used as a RAM cell. Node 34 would normally be a bit line connection of a memory array, with node 35 being the complementary bit line connection. Transistor 2 is the output device for node 34. Transistor 4 has the emitter and base shorted together, and along with its built-in base resistor acts as a load for transistor 3. Fig. 2 shows a cross-section of about one-half of the cell, and corresponds to the area within the dotted lines of Fig. 1. Region 1 of Fig. 2 is an N+ subcollector common to the collectors of transistors 2, 3 and 4 of Fig. 1. N+ region 9 is a reach-through to connect subcollector 1 to metal region 10. Region 10 corresponds to node 11 of Fig. 1. Regions 5, 6 and 7 are recessed oxide to isolate other regions. N- region 8 and metal region 13 form Schottky barrier diode 14 of Fig. 1 at region 12 of Fig. 2. Metal 13 also corresponds to node 23 of Fig. 1. This node is normally connected to the top end of the word line in a memory array...