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Fault Model of a Non-Scannable Latch Circuit

IP.com Disclosure Number: IPCOM000059658D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Wu, DM: AUTHOR

Abstract

In a general-purpose register, a typical latch circuit used is very difficult to test for all DC defects. A new model logic representation for fault testing the latch circuit is described which will detect all common DC defects. Fig. 1 is a schematic diagram of a latch circuit which is part of a general-purpose register. The key elements of interest are transistors 1 through 6 and the ports 7 through 15. Fig. 2 shows a logic diagram for fault-detection purposes which is equivalent functionally to the circuit of Fig. 1. The ports are numbered the same and correspond to those in Fig. 1. Although Fig. 2 represents the logic of Fig. 1 when all elements are working properly, it cannot be used to detect all single common faults which may be present in the circuit. Specifically, the Fig. 2 diagram cannot be used to detect: 1.

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Fault Model of a Non-Scannable Latch Circuit

In a general-purpose register, a typical latch circuit used is very difficult to test for all DC defects. A new model logic representation for fault testing the latch circuit is described which will detect all common DC defects. Fig. 1 is a schematic diagram of a latch circuit which is part of a general-purpose register. The key elements of interest are transistors 1 through 6 and the ports 7 through
15. Fig. 2 shows a logic diagram for fault-detection purposes which is equivalent functionally to the circuit of Fig. 1. The ports are numbered the same and correspond to those in Fig. 1. Although Fig. 2 represents the logic of Fig. 1 when all elements are working properly, it cannot be used to detect all single common faults which may be present in the circuit. Specifically, the Fig. 2 diagram cannot be used to detect: 1. transistor 1 collector-emitter short 2. transistor 2 collector- emitter short 3. transistor 1 base-collector short 4. transistor 2 base-collector short 5. transistor 4 open-emitter connection Fig. 3 is an improved fault detection logic diagram which will permit detecting the above faults which are missed by the Fig. 2 arrangement. It may be noted that the diagram has two additional ports 16 and 17 which are not contained in Figs. 1 or 2. This does not require extra physical inputs to the actual circuit of Fig. 1, but is an artifice used in devising the proper test patterns to detect the above faults. The...