Browse Prior Art Database

Submicron Isolation Trenches in Silicon

IP.com Disclosure Number: IPCOM000059664D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Grossman, BM: AUTHOR

Abstract

Very small dimension trenches of the order of 0.25 micron width and several microns deep may be made in silicon substrates by depositing a small dimension pattern member of removable material against an edge, chemically converting the surface adjacent to the pattern member with a reaction that progresses under part of the pattern member, leaving an even smaller dimension, removing the pattern member, and using the smaller dimension as an etchant opening for trench formation. The technique is illustrated and described in the following 10 steps: (1) Begin with a multilayered structure consisting of a thick layer (1000 to 4000 ˜) of SiO2, a 500 to 2000 ˜ layer of polysilicon, 1.0 to 2.0 mm of photoresist, and 200 to 500 ˜ of low temperature plasma- deposited SiO2, all on top of a silicon substrate, as shown in Fig. 1.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 64% of the total text.

Page 1 of 2

Submicron Isolation Trenches in Silicon

Very small dimension trenches of the order of 0.25 micron width and several microns deep may be made in silicon substrates by depositing a small dimension pattern member of removable material against an edge, chemically converting the surface adjacent to the pattern member with a reaction that progresses under part of the pattern member, leaving an even smaller dimension, removing the pattern member, and using the smaller dimension as an etchant opening for trench formation. The technique is illustrated and described in the following 10 steps: (1) Begin with a multilayered structure consisting of a thick layer (1000 to 4000 ~) of SiO2, a 500 to 2000 ~ layer of polysilicon, 1.0 to 2.0 mm of photoresist, and 200 to 500 ~ of low temperature plasma- deposited SiO2, all on top of a silicon substrate, as shown in Fig. 1. (2) Pattern an edge in the plasma- deposited SiO2 with a CF4 reactive ion etch (RIE), as shown in Fig. 2. (3) Etch a vertical step in the photoresist layer with an O2 RIE using the patterned SiO2 layer as a mask. Then, strip the SiO2 mask with a buffered HF solution, as shown in Fig. 3. (4) Conformally deposit 4000 to 6000 ~ of plasma Si3N4, at low temperature (< 300OEC), over the photoresist step, as shown in Fig. 4. (5) Clear the horizontal surface of Si3N4 by a CF4 RIE, leaving a sidewall of Si3N4 abutting the vertical surface of the photoresist step, as shown in Fig. 5. (6) Strip photoresist and thermally gro...