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High Performance Single-Ended Multiport CMOS Memory Cell

IP.com Disclosure Number: IPCOM000059670D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

Braceras, GM: AUTHOR [+2]

Abstract

A high density and high performance multi-port memory cell made possible by the use of a pseudo sense line in place of a full dual-ended sense line is described. The storage cell and sensing circuit shown in Fig. 1 use single- bit lines Out 1 and Out 2 for each signal. The signal is generated from the comparison of two voltage levels made possible by the inclusion of Sense Line which simulates a bit line pair. By using device TL to precisely match the loading seen on Out 1 and Out 2 lines, a voltage difference between the Out line and Sense line at the time the Set signal is fired determines the amount of signal available across the Sense Amplifier (SA). The polarity of this voltage determines the contents of the cell.

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High Performance Single-Ended Multiport CMOS Memory Cell

A high density and high performance multi-port memory cell made possible by the use of a pseudo sense line in place of a full dual-ended sense line is described. The storage cell and sensing circuit shown in Fig. 1 use single- bit lines Out 1 and Out 2 for each signal. The signal is generated from the comparison of two voltage levels made possible by the inclusion of Sense Line which simulates a bit line pair. By using device TL to precisely match the loading seen on Out 1 and Out 2 lines, a voltage difference between the Out line and Sense line at the time the Set signal is fired determines the amount of signal available across the Sense Amplifier (SA). The polarity of this voltage determines the contents of the cell. During the Read operation, the rising Simulated Word Line (SWL) matches Word Lines PR1 and PR2 and causes the Sense Line to be pulled down to ground through device TS . Device TS is designed such that the Sense Line falls at half the slope of a falling Out 1 or Out 2 line, and the voltage difference and polarity is sensed as a "1" or "0" signal (Fig. 2). By using single-bit lines for each signal, a considerable area savings is realized with this design. To trigger the Sense Latch, all that is needed is minimal signal development between the Out and Sense lines which results in considerable time savings. Hence, a dense and high performance multi-port CMOS (Complementary Metal Oxide Semiconduct...