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Multi-Level Interrupt Acknowledgement Circuit

IP.com Disclosure Number: IPCOM000059673D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Millas, RJ: AUTHOR [+3]

Abstract

A technique is described whereby an interrupt acknowledge controller is used in conjunction with microprocessors which have been designed to allow external interrupt lines to be programmable. The interrupt acknowledge controller utilizes programmable interrupt acknowledge registers so as to control large numbers of bus lines used in interrupt adapter circuits. This enables the controller to control the interrupts so as to reduce the number of input/output (I/O) interface lines. Microprocessor systems often require large numbers of bus lines to interface to adapter card circuits. The bus lines therefore must be optimized so as to physically place bus lines onto the interface connectors.

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Multi-Level Interrupt Acknowledgement Circuit

A technique is described whereby an interrupt acknowledge controller is used in conjunction with microprocessors which have been designed to allow external interrupt lines to be programmable. The interrupt acknowledge controller utilizes programmable interrupt acknowledge registers so as to control large numbers of bus lines used in interrupt adapter circuits. This enables the controller to control the interrupts so as to reduce the number of input/output (I/O) interface lines. Microprocessor systems often require large numbers of bus lines to interface to adapter card circuits. The bus lines therefore must be optimized so as to physically place bus lines onto the interface connectors. The technique described herein provides a means of reducing the number of bus lines by providing interrupt acknowledgement control circuitry for programmable interrupt microprocessor systems. The interrupt acknowledge controller was designed to be used with the Motorola 68000 microprocessor; however, this concept could be used with other microprocessors. The design incorporates programmable external interrupt lines which can be programmed to interrupt on levels 1 through
7. Normally, interrupt lines are wired to a fixed level. In the case of the Motorola 68000, during an interrupt acknowledge cycle address lines A1, A2 and A3 represent the interrupt level being serviced. When interrupts are hard wired, interrupt adapter circuitry will distinguish which interru...