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Reliability and Serviceability Enhancement for Multi-Bit Array Chip Storage

IP.com Disclosure Number: IPCOM000059684D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Ruane, AJ: AUTHOR [+2]

Abstract

Multi-bit errors that are caused by a chip kill create an uncorrectable error situation. A redundant bit implementation can be used to replace bad bits on a chip for chip basis in storage designs that have an array with more that one bit per chip in an error checking and correcting (ECC) word. However, redundant bit implementation causes system degradation by placing additional delay in the ECC path due to packet correction circuitry. In situations where array failure caused by chip kills is significant, redundant bit implementation will cause substantial system degradation.

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Reliability and Serviceability Enhancement for Multi-Bit Array Chip Storage

Multi-bit errors that are caused by a chip kill create an uncorrectable error situation. A redundant bit implementation can be used to replace bad bits on a chip for chip basis in storage designs that have an array with more that one bit per chip in an error checking and correcting (ECC) word. However, redundant bit implementation causes system degradation by placing additional delay in the ECC path due to packet correction circuitry. In situations where array failure caused by chip kills is significant, redundant bit implementation will cause substantial system degradation. A design that allows chip kills to be removed and dual failures to be removed if neither is a chip kill is accomplished by partitioning the redundant sector in the following manner:

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A 4 meg card with an 8-byte interface would require 36 modules for the data and ECC, and one module for the redundant bits. The multi-bit modules should be dotted, e.g., a 4-bit module to two bits with each bit in a redundant bit segment (Fig. 1). Each segment is across 18 bits. A 2 meg card in the same system would have 18 modules and one redundant module. Each bit would be wired to a segment with a redundant bit (Fig. 2). The criteria for this implementation is that there are no chip kills and only one failure per redundant segment.

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