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Dynamic Error Checking and Correcting ON/OFF Mechanism

IP.com Disclosure Number: IPCOM000059697D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Boguski, MJ: AUTHOR [+6]

Abstract

There are systems that allow error checking and correcting (ECC) logic enable or disable for diagnostic function. However, in a normal operating environment toggling from one mode to the other would cause double-bit errors, due to improper initialization of the check bits. To overcome this problem, the whole memory must be initialized with ECC enabled before any read cycles are performed by the system. A method of selecting or bypassing ECC dynamically, without the need to initialize the memory, is described in the following. Microprocessors, such as a Motorola 68000, require an input response to a memory bus cycle to terminate normally (i.e., valid data available at the processor bus on a read cycle or data accepted by the memory on a write cycle) or abort the cycle in case of any exception conditions.

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Dynamic Error Checking and Correcting ON/OFF Mechanism

There are systems that allow error checking and correcting (ECC) logic enable or disable for diagnostic function. However, in a normal operating environment toggling from one mode to the other would cause double-bit errors, due to improper initialization of the check bits. To overcome this problem, the whole memory must be initialized with ECC enabled before any read cycles are performed by the system. A method of selecting or bypassing ECC dynamically, without the need to initialize the memory, is described in the following. Microprocessors, such as a Motorola 68000, require an input response to a memory bus cycle to terminate normally (i.e., valid data available at the processor bus on a read cycle or data accepted by the memory on a write cycle) or abort the cycle in case of any exception conditions. This means a response signal cannot be generated until all the exceptions are resolved. The worst-case time to check and correct a single-bit error is greater than 100 nanoseconds, which is greater than one processor clock cycle. This would result in an extra wait state (Fig. 1) on every memory read cycle. However, if an early response is given to the processor before the checking and correction is completed, this additional wait state can be eliminated. If a single- bit error is detected later in the cycle, an interrupt or exception can be generated either for system recovery or abend. In single-user desk top...