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Hardware Assist for Program Event Recording

IP.com Disclosure Number: IPCOM000059699D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Bruetsch, BJ: AUTHOR

Abstract

Program event recording (PER) is done by a microcode that requires an interrupt for every instruction (to ascertain that the address used is the address of the event of interest) which causes system degradation. A hardware assist permits a trap to be taken only when the address being used is within the 2- or 4K-page boundary of the address PER is enabled for. The trap will then cause an interrupt where the code will determine whether the address is the address of interest. This narrowing down to a 2 or 4K page before taking the interrupt will decrease the number of interrupts which will improve performance when PER is active. To select the 2 or 4K page of interest, a bit will be set in the directory look-aside table (DLAT) 1 for every 2 or 4K page that PER is enabled for.

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Hardware Assist for Program Event Recording

Program event recording (PER) is done by a microcode that requires an interrupt for every instruction (to ascertain that the address used is the address of the event of interest) which causes system degradation. A hardware assist permits a trap to be taken only when the address being used is within the 2- or 4K-page boundary of the address PER is enabled for. The trap will then cause an interrupt where the code will determine whether the address is the address of interest. This narrowing down to a 2 or 4K page before taking the interrupt will decrease the number of interrupts which will improve performance when PER is active. To select the 2 or 4K page of interest, a bit will be set in the directory look- aside table (DLAT) 1 for every 2 or 4K page that PER is enabled for. Whenever a storage alteration or instruction fetch is done for the page, the bit will be read out and, if PER is enabled for that type of access, a trap will be taken. The interrupt bit in the trap will be set for the event and a DLAT hit/miss will have no effect on the trap. An external register, controlled by microcode, is used to store the type of PER events being monitored.

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