Browse Prior Art Database

High Speed Depletion-Mode Read-Only Storage Array

IP.com Disclosure Number: IPCOM000059701D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 67K

Publishing Venue

IBM

Related People

Kalter, HL: AUTHOR [+2]

Abstract

This MOSFET read-only storage (ROS) array uses NOR logic and provides access times approaching those of bipolar circuits when word and bit access lines are fabricated with metal conductors rather than with polysilicon or diffusions. Fig. 1 shows a group of four memory cells in a depletion-mode NOR ROS array. Each memory device is coupled to three signal lines crossing the memory array. A word line WL provides an accessing signal to a selected column of memory devices while a bit line BL and a return line R are used to determine whether a particular device has had its channel region ion implanted to convert it from a normal enhancement mode device to a depletion-mode device. Memory devices T11 and T22 are shown as depletion-mode devices. Fig. 2 shows the pulse program for the signal voltages used in the array of Fig. 1.

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High Speed Depletion-Mode Read-Only Storage Array

This MOSFET read-only storage (ROS) array uses NOR logic and provides access times approaching those of bipolar circuits when word and bit access lines are fabricated with metal conductors rather than with polysilicon or diffusions. Fig. 1 shows a group of four memory cells in a depletion-mode NOR ROS array. Each memory device is coupled to three signal lines crossing the memory array. A word line WL provides an accessing signal to a selected column of memory devices while a bit line BL and a return line R are used to determine whether a particular device has had its channel region ion implanted to convert it from a normal enhancement mode device to a depletion-mode device. Memory devices T11 and T22 are shown as depletion-mode devices. Fig. 2 shows the pulse program for the signal voltages used in the array of Fig. 1. A word line, for example, WL1, is selected by driving it to a high logic level V. Unselected word lines remain at the low logic level. The return lines R1 and R2 are biased at a positive potential VI, for n-channel devices, to prevent the conduction of depletion devices on unselected word lines. VI is selected to be within one enhancement device threshold voltage drop below high logic level V to prevent selected enhancement devices from conducting when a word line is selected. Fig. 2 shows that the bit line associated with a selected enhancement device remains unchanged. When a depletion device is selected, the memory transistor conducts to discharge the precharged bit line to VI. Fig. 3 illustrates another depletion-mode NOR ROS memory array in which the gate electrode of each memory device is connected permanently to a fixed potential, ground. A word line WL is connected to the source electrode of each device, and a bit line BL is connected to the drain electrode. Programming logical "1's" and "0's" is accomplished as in the Fig. 1 circuit, by selectively providing depletion- and ...