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Field-Effect Transistor Output Driver

IP.com Disclosure Number: IPCOM000059702D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 74K

Publishing Venue

IBM

Related People

Kalter, HL: AUTHOR

Abstract

The layout of this field-effect transistor is designed to use a minimum of semiconductor area by the use of hexagonal packing in which device elements are located in a pattern of regular hexagons. The transistor has a high-current driving capacity. The transistor is formed within the perimeter of recessed field oxide 10 and includes a polysilicon gate electrode structure 12 formed as an open lattice of intersecting regular hexagons which act as a self-aligned mask for ion implanted source and drain regions 14 and 16. After passivation of gate electrode 12 and etching of contact holes 18, 20 and 22 for source, drain and gate contacts, a metal layer is deposited and defined to provide electrodes 24, 26 and 28 which provide contact through vias 18', 20' and 22'.

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Field-Effect Transistor Output Driver

The layout of this field-effect transistor is designed to use a minimum of semiconductor area by the use of hexagonal packing in which device elements are located in a pattern of regular hexagons. The transistor has a high-current driving capacity. The transistor is formed within the perimeter of recessed field oxide 10 and includes a polysilicon gate electrode structure 12 formed as an open lattice of intersecting regular hexagons which act as a self-aligned mask for ion implanted source and drain regions 14 and 16. After passivation of gate electrode 12 and etching of contact holes 18, 20 and 22 for source, drain and gate contacts, a metal layer is deposited and defined to provide electrodes 24, 26 and 28 which provide contact through vias 18', 20' and 22'. Use of this hexagonal layout provides more precise control over device width-to-length ratio than that provided by linear interdigitated electrode drivers because the channel width is not subject to dimensional tolerance due to the closed nature of the sub-devices formed.

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