Browse Prior Art Database

Prefetching Using a Pageable Branch History Table

IP.com Disclosure Number: IPCOM000059709D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Pomerene, JH: AUTHOR [+5]

Abstract

Prefetching of cache lines using a pageable branch history table (PBHT) improves machine performance through better cache miss ratio and fewer pipeline disruptions. A branch history table gives probable resolution of branches. Using these probable resolutions, it is possible to partition a cache line into regions and determine for each region the next cache line to be used. An example of this partitioning is given in Fig. 1, which shows a cache line N containing four branches (1), (2), (3), (4). Taken branches (1) and (3) have targets (TA) within the line, while taken branches (2) and (4) branch to addresses in cache line A and B, respectively. A branch history table only records taken branches and, by implication, the absence of a branch address indicates that the branch is not taken. The segment (Fig.

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Prefetching Using a Pageable Branch History Table

Prefetching of cache lines using a pageable branch history table (PBHT) improves machine performance through better cache miss ratio and fewer pipeline disruptions. A branch history table gives probable resolution of branches. Using these probable resolutions, it is possible to partition a cache line into regions and determine for each region the next cache line to be used. An example of this partitioning is given in Fig. 1, which shows a cache line N containing four branches (1), (2), (3), (4). Taken branches (1) and (3) have targets (TA) within the line, while taken branches (2) and (4) branch to addresses in cache line A and B, respectively. A branch history table only records taken branches and, by implication, the absence of a branch address indicates that the branch is not taken. The segment (Fig. 2) of a PBHT contains four entries. These four entries can be considered to be in sorted order by branch address (BA). Each entry is extended to include indicative information as to the exit from the line. The four branches partition the cache line into five regions. If the line is entered in the first region, the probable cache line to be accessed is line N + 1, the next sequential line (NSL). If cache line N is entered in the second region, line A is accessed next. A secondary two-level cache directory (I-Shadow) contains the same number of congruence classes as the cache. Each entry in the I-Shadow contains the...